Syntax of gfx90a Instructions — LLVM 22.1.8 documentation

# Syntax of gfx90a Instructions

## Introduction

This document describes the syntax of gfx90a instructions.

## Notation

Notation used in this document is explained here.

## Overview

An overview of generic syntax and other features of AMDGPU instructions may be found in this document.

## Instructions

### DS

    INSTRUCTION                    DST         SRC0      SRC1      SRC2           MODIFIERS
    —————————————————————————————————————————————————————————————————————————————————————————————————
    ds_add_f32                                 vaddr,    vdata                    offset gds
    ds_add_f64                                 vaddr,    vdata                    offset gds
    ds_add_rtn_f32                 vdst,       vaddr,    vdata                    offset gds
    ds_add_rtn_f64                 vdst,       vaddr,    vdata                    offset gds
    ds_add_rtn_u32                 vdst,       vaddr,    vdata                    offset gds
    ds_add_rtn_u64                 vdst,       vaddr,    vdata                    offset gds
    ds_add_u32                                 vaddr,    vdata                    offset gds
    ds_add_u64                                 vaddr,    vdata                    offset gds
    ds_and_b32                                 vaddr,    vdata                    offset gds
    ds_and_b64                                 vaddr,    vdata                    offset gds
    ds_and_rtn_b32                 vdst,       vaddr,    vdata                    offset gds
    ds_and_rtn_b64                 vdst,       vaddr,    vdata                    offset gds
    ds_append                      vdst                                           offset gds
    ds_bpermute_b32                vdst,       vaddr,    vdata                    offset
    ds_cmpst_b32                               vaddr,    vdata0,   vdata1         offset gds
    ds_cmpst_b64                               vaddr,    vdata0,   vdata1         offset gds
    ds_cmpst_f32                               vaddr,    vdata0,   vdata1         offset gds
    ds_cmpst_f64                               vaddr,    vdata0,   vdata1         offset gds
    ds_cmpst_rtn_b32               vdst,       vaddr,    vdata0,   vdata1         offset gds
    ds_cmpst_rtn_b64               vdst,       vaddr,    vdata0,   vdata1         offset gds
    ds_cmpst_rtn_f32               vdst,       vaddr,    vdata0,   vdata1         offset gds
    ds_cmpst_rtn_f64               vdst,       vaddr,    vdata0,   vdata1         offset gds
    ds_condxchg32_rtn_b64          vdst,       vaddr,    vdata                    offset gds
    ds_consume                     vdst                                           offset gds
    ds_dec_rtn_u32                 vdst,       vaddr,    vdata                    offset gds
    ds_dec_rtn_u64                 vdst,       vaddr,    vdata                    offset gds
    ds_dec_u32                                 vaddr,    vdata                    offset gds
    ds_dec_u64                                 vaddr,    vdata                    offset gds
    ds_gws_barrier                             vdata                              offset gds
    ds_gws_init                                vdata                              offset gds
    ds_gws_sema_br                             vdata                              offset gds
    ds_gws_sema_p                                                                 offset gds
    ds_gws_sema_release_all                                                       offset gds
    ds_gws_sema_v                                                                 offset gds
    ds_inc_rtn_u32                 vdst,       vaddr,    vdata                    offset gds
    ds_inc_rtn_u64                 vdst,       vaddr,    vdata                    offset gds
    ds_inc_u32                                 vaddr,    vdata                    offset gds
    ds_inc_u64                                 vaddr,    vdata                    offset gds
    ds_max_f32                                 vaddr,    vdata                    offset gds
    ds_max_f64                                 vaddr,    vdata                    offset gds
    ds_max_i32                                 vaddr,    vdata                    offset gds
    ds_max_i64                                 vaddr,    vdata                    offset gds
    ds_max_rtn_f32                 vdst,       vaddr,    vdata                    offset gds
    ds_max_rtn_f64                 vdst,       vaddr,    vdata                    offset gds
    ds_max_rtn_i32                 vdst,       vaddr,    vdata                    offset gds
    ds_max_rtn_i64                 vdst,       vaddr,    vdata                    offset gds
    ds_max_rtn_u32                 vdst,       vaddr,    vdata                    offset gds
    ds_max_rtn_u64                 vdst,       vaddr,    vdata                    offset gds
    ds_max_u32                                 vaddr,    vdata                    offset gds
    ds_max_u64                                 vaddr,    vdata                    offset gds
    ds_min_f32                                 vaddr,    vdata                    offset gds
    ds_min_f64                                 vaddr,    vdata                    offset gds
    ds_min_i32                                 vaddr,    vdata                    offset gds
    ds_min_i64                                 vaddr,    vdata                    offset gds
    ds_min_rtn_f32                 vdst,       vaddr,    vdata                    offset gds
    ds_min_rtn_f64                 vdst,       vaddr,    vdata                    offset gds
    ds_min_rtn_i32                 vdst,       vaddr,    vdata                    offset gds
    ds_min_rtn_i64                 vdst,       vaddr,    vdata                    offset gds
    ds_min_rtn_u32                 vdst,       vaddr,    vdata                    offset gds
    ds_min_rtn_u64                 vdst,       vaddr,    vdata                    offset gds
    ds_min_u32                                 vaddr,    vdata                    offset gds
    ds_min_u64                                 vaddr,    vdata                    offset gds
    ds_mskor_b32                               vaddr,    vdata0,   vdata1         offset gds
    ds_mskor_b64                               vaddr,    vdata0,   vdata1         offset gds
    ds_mskor_rtn_b32               vdst,       vaddr,    vdata0,   vdata1         offset gds
    ds_mskor_rtn_b64               vdst,       vaddr,    vdata0,   vdata1         offset gds
    ds_nop
    ds_or_b32                                  vaddr,    vdata                    offset gds
    ds_or_b64                                  vaddr,    vdata                    offset gds
    ds_or_rtn_b32                  vdst,       vaddr,    vdata                    offset gds
    ds_or_rtn_b64                  vdst,       vaddr,    vdata                    offset gds
    ds_permute_b32                 vdst,       vaddr,    vdata                    offset
    ds_read2_b32                   vdst:b32x2, vaddr                              offset0 offset1 gds
    ds_read2_b64                   vdst:b64x2, vaddr                              offset0 offset1 gds
    ds_read2st64_b32               vdst:b32x2, vaddr                              offset0 offset1 gds
    ds_read2st64_b64               vdst:b64x2, vaddr                              offset0 offset1 gds
    ds_read_addtid_b32             vdst                                           offset gds
    ds_read_b128                   vdst,       vaddr                              offset gds
    ds_read_b32                    vdst,       vaddr                              offset gds
    ds_read_b64                    vdst,       vaddr                              offset gds
    ds_read_b96                    vdst,       vaddr                              offset gds
    ds_read_i16                    vdst,       vaddr                              offset gds
    ds_read_i8                     vdst,       vaddr                              offset gds
    ds_read_i8_d16                 vdst,       vaddr                              offset gds
    ds_read_i8_d16_hi              vdst,       vaddr                              offset gds
    ds_read_u16                    vdst,       vaddr                              offset gds
    ds_read_u16_d16                vdst,       vaddr                              offset gds
    ds_read_u16_d16_hi             vdst,       vaddr                              offset gds
    ds_read_u8                     vdst,       vaddr                              offset gds
    ds_read_u8_d16                 vdst,       vaddr                              offset gds
    ds_read_u8_d16_hi              vdst,       vaddr                              offset gds
    ds_rsub_rtn_u32                vdst,       vaddr,    vdata                    offset gds
    ds_rsub_rtn_u64                vdst,       vaddr,    vdata                    offset gds
    ds_rsub_u32                                vaddr,    vdata                    offset gds
    ds_rsub_u64                                vaddr,    vdata                    offset gds
    ds_sub_rtn_u32                 vdst,       vaddr,    vdata                    offset gds
    ds_sub_rtn_u64                 vdst,       vaddr,    vdata                    offset gds
    ds_sub_u32                                 vaddr,    vdata                    offset gds
    ds_sub_u64                                 vaddr,    vdata                    offset gds
    ds_swizzle_b32                 vdst,       vaddr                              pattern gds
    ds_wrap_rtn_b32                vdst,       vaddr,    vdata0,   vdata1         offset gds
    ds_write2_b32                              vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_write2_b64                              vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_write2st64_b32                          vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_write2st64_b64                          vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_write_addtid_b32                        vdata                              offset gds
    ds_write_b128                              vaddr,    vdata                    offset gds
    ds_write_b16                               vaddr,    vdata                    offset gds
    ds_write_b16_d16_hi                        vaddr,    vdata                    offset gds
    ds_write_b32                               vaddr,    vdata                    offset gds
    ds_write_b64                               vaddr,    vdata                    offset gds
    ds_write_b8                                vaddr,    vdata                    offset gds
    ds_write_b8_d16_hi                         vaddr,    vdata                    offset gds
    ds_write_b96                               vaddr,    vdata                    offset gds
    ds_wrxchg2_rtn_b32             vdst:b32x2, vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_wrxchg2_rtn_b64             vdst:b64x2, vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_wrxchg2st64_rtn_b32         vdst:b32x2, vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_wrxchg2st64_rtn_b64         vdst:b64x2, vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_wrxchg_rtn_b32              vdst,       vaddr,    vdata                    offset gds
    ds_wrxchg_rtn_b64              vdst,       vaddr,    vdata                    offset gds
    ds_xor_b32                                 vaddr,    vdata                    offset gds
    ds_xor_b64                                 vaddr,    vdata                    offset gds
    ds_xor_rtn_b32                 vdst,       vaddr,    vdata                    offset gds
    ds_xor_rtn_b64                 vdst,       vaddr,    vdata                    offset gds

### FLAT

    INSTRUCTION                    DST           SRC0      SRC1         SRC2       MODIFIERS
    ————————————————————————————————————————————————————————————————————————————————————————————————————
    flat_atomic_add                vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_atomic_add_f64            vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_atomic_add_x2             vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_atomic_and                vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_atomic_and_x2             vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_atomic_cmpswap            vdst:opt,     vaddr,    vdata:b32x2             offset12 glc slc
    flat_atomic_cmpswap_x2         vdst:opt,     vaddr,    vdata:b64x2             offset12 glc slc
    flat_atomic_dec                vdst:opt:u32, vaddr,    vdata:u32               offset12 glc slc
    flat_atomic_dec_x2             vdst:opt:u64, vaddr,    vdata:u64               offset12 glc slc
    flat_atomic_inc                vdst:opt:u32, vaddr,    vdata:u32               offset12 glc slc
    flat_atomic_inc_x2             vdst:opt:u64, vaddr,    vdata:u64               offset12 glc slc
    flat_atomic_max_f64            vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_atomic_min_f64            vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_atomic_or                 vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_atomic_or_x2              vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_atomic_smax               vdst:opt:i32, vaddr,    vdata:i32               offset12 glc slc
    flat_atomic_smax_x2            vdst:opt:i64, vaddr,    vdata:i64               offset12 glc slc
    flat_atomic_smin               vdst:opt:i32, vaddr,    vdata:i32               offset12 glc slc
    flat_atomic_smin_x2            vdst:opt:i64, vaddr,    vdata:i64               offset12 glc slc
    flat_atomic_sub                vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_atomic_sub_x2             vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_atomic_swap               vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_atomic_swap_x2            vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_atomic_umax               vdst:opt:u32, vaddr,    vdata:u32               offset12 glc slc
    flat_atomic_umax_x2            vdst:opt:u64, vaddr,    vdata:u64               offset12 glc slc
    flat_atomic_umin               vdst:opt:u32, vaddr,    vdata:u32               offset12 glc slc
    flat_atomic_umin_x2            vdst:opt:u64, vaddr,    vdata:u64               offset12 glc slc
    flat_atomic_xor                vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_atomic_xor_x2             vdst:opt,     vaddr,    vdata                   offset12 glc slc
    flat_load_dword                vdst,         vaddr                             offset12 glc slc
    flat_load_dwordx2              vdst,         vaddr                             offset12 glc slc
    flat_load_dwordx3              vdst,         vaddr                             offset12 glc slc
    flat_load_dwordx4              vdst,         vaddr                             offset12 glc slc
    flat_load_sbyte                vdst,         vaddr                             offset12 glc slc
    flat_load_sbyte_d16            vdst,         vaddr                             offset12 glc slc
    flat_load_sbyte_d16_hi         vdst,         vaddr                             offset12 glc slc
    flat_load_short_d16            vdst,         vaddr                             offset12 glc slc
    flat_load_short_d16_hi         vdst,         vaddr                             offset12 glc slc
    flat_load_sshort               vdst,         vaddr                             offset12 glc slc
    flat_load_ubyte                vdst,         vaddr                             offset12 glc slc
    flat_load_ubyte_d16            vdst,         vaddr                             offset12 glc slc
    flat_load_ubyte_d16_hi         vdst,         vaddr                             offset12 glc slc
    flat_load_ushort               vdst,         vaddr                             offset12 glc slc
    flat_store_byte                              vaddr,    vdata                   offset12 glc slc
    flat_store_byte_d16_hi                       vaddr,    vdata                   offset12 glc slc
    flat_store_dword                             vaddr,    vdata                   offset12 glc slc
    flat_store_dwordx2                           vaddr,    vdata                   offset12 glc slc
    flat_store_dwordx3                           vaddr,    vdata                   offset12 glc slc
    flat_store_dwordx4                           vaddr,    vdata                   offset12 glc slc
    flat_store_short                             vaddr,    vdata                   offset12 glc slc
    flat_store_short_d16_hi                      vaddr,    vdata                   offset12 glc slc
    global_atomic_add              vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_add_f32          vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_add_f64          vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_add_x2           vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_and              vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_and_x2           vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_cmpswap          vdst:opt,     vaddr,    vdata:b32x2, saddr      offset13s glc slc
    global_atomic_cmpswap_x2       vdst:opt,     vaddr,    vdata:b64x2, saddr      offset13s glc slc
    global_atomic_dec              vdst:opt:u32, vaddr,    vdata:u32,   saddr      offset13s glc slc
    global_atomic_dec_x2           vdst:opt:u64, vaddr,    vdata:u64,   saddr      offset13s glc slc
    global_atomic_inc              vdst:opt:u32, vaddr,    vdata:u32,   saddr      offset13s glc slc
    global_atomic_inc_x2           vdst:opt:u64, vaddr,    vdata:u64,   saddr      offset13s glc slc
    global_atomic_max_f64          vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_min_f64          vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_or               vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_or_x2            vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_pk_add_f16       vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_smax             vdst:opt:i32, vaddr,    vdata:i32,   saddr      offset13s glc slc
    global_atomic_smax_x2          vdst:opt:i64, vaddr,    vdata:i64,   saddr      offset13s glc slc
    global_atomic_smin             vdst:opt:i32, vaddr,    vdata:i32,   saddr      offset13s glc slc
    global_atomic_smin_x2          vdst:opt:i64, vaddr,    vdata:i64,   saddr      offset13s glc slc
    global_atomic_sub              vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_sub_x2           vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_swap             vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_swap_x2          vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_umax             vdst:opt:u32, vaddr,    vdata:u32,   saddr      offset13s glc slc
    global_atomic_umax_x2          vdst:opt:u64, vaddr,    vdata:u64,   saddr      offset13s glc slc
    global_atomic_umin             vdst:opt:u32, vaddr,    vdata:u32,   saddr      offset13s glc slc
    global_atomic_umin_x2          vdst:opt:u64, vaddr,    vdata:u64,   saddr      offset13s glc slc
    global_atomic_xor              vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_atomic_xor_x2           vdst:opt,     vaddr,    vdata,       saddr      offset13s glc slc
    global_load_dword              vdst:opt,     vaddr,    saddr                   offset13s glc slc lds
    global_load_dwordx2            vdst,         vaddr,    saddr                   offset13s glc slc
    global_load_dwordx3            vdst,         vaddr,    saddr                   offset13s glc slc
    global_load_dwordx4            vdst,         vaddr,    saddr                   offset13s glc slc
    global_load_sbyte              vdst:opt,     vaddr,    saddr                   offset13s glc slc lds
    global_load_sbyte_d16          vdst,         vaddr,    saddr                   offset13s glc slc
    global_load_sbyte_d16_hi       vdst,         vaddr,    saddr                   offset13s glc slc
    global_load_short_d16          vdst,         vaddr,    saddr                   offset13s glc slc
    global_load_short_d16_hi       vdst,         vaddr,    saddr                   offset13s glc slc
    global_load_sshort             vdst:opt,     vaddr,    saddr                   offset13s glc slc lds
    global_load_ubyte              vdst:opt,     vaddr,    saddr                   offset13s glc slc lds
    global_load_ubyte_d16          vdst,         vaddr,    saddr                   offset13s glc slc
    global_load_ubyte_d16_hi       vdst,         vaddr,    saddr                   offset13s glc slc
    global_load_ushort             vdst:opt,     vaddr,    saddr                   offset13s glc slc lds
    global_store_byte                            vaddr,    vdata,       saddr      offset13s glc slc
    global_store_byte_d16_hi                     vaddr,    vdata,       saddr      offset13s glc slc
    global_store_dword                           vaddr,    vdata,       saddr      offset13s glc slc
    global_store_dwordx2                         vaddr,    vdata,       saddr      offset13s glc slc
    global_store_dwordx3                         vaddr,    vdata,       saddr      offset13s glc slc
    global_store_dwordx4                         vaddr,    vdata,       saddr      offset13s glc slc
    global_store_short                           vaddr,    vdata,       saddr      offset13s glc slc
    global_store_short_d16_hi                    vaddr,    vdata,       saddr      offset13s glc slc
    scratch_load_dword             vdst:opt,     vaddr,    saddr                   offset13s glc slc lds
    scratch_load_dwordx2           vdst,         vaddr,    saddr                   offset13s glc slc
    scratch_load_dwordx3           vdst,         vaddr,    saddr                   offset13s glc slc
    scratch_load_dwordx4           vdst,         vaddr,    saddr                   offset13s glc slc
    scratch_load_sbyte             vdst:opt,     vaddr,    saddr                   offset13s glc slc lds
    scratch_load_sbyte_d16         vdst,         vaddr,    saddr                   offset13s glc slc
    scratch_load_sbyte_d16_hi      vdst,         vaddr,    saddr                   offset13s glc slc
    scratch_load_short_d16         vdst,         vaddr,    saddr                   offset13s glc slc
    scratch_load_short_d16_hi      vdst,         vaddr,    saddr                   offset13s glc slc
    scratch_load_sshort            vdst:opt,     vaddr,    saddr                   offset13s glc slc lds
    scratch_load_ubyte             vdst:opt,     vaddr,    saddr                   offset13s glc slc lds
    scratch_load_ubyte_d16         vdst,         vaddr,    saddr                   offset13s glc slc
    scratch_load_ubyte_d16_hi      vdst,         vaddr,    saddr                   offset13s glc slc
    scratch_load_ushort            vdst:opt,     vaddr,    saddr                   offset13s glc slc lds
    scratch_store_byte                           vaddr,    vdata,       saddr      offset13s glc slc
    scratch_store_byte_d16_hi                    vaddr,    vdata,       saddr      offset13s glc slc
    scratch_store_dword                          vaddr,    vdata,       saddr      offset13s glc slc
    scratch_store_dwordx2                        vaddr,    vdata,       saddr      offset13s glc slc
    scratch_store_dwordx3                        vaddr,    vdata,       saddr      offset13s glc slc
    scratch_store_dwordx4                        vaddr,    vdata,       saddr      offset13s glc slc
    scratch_store_short                          vaddr,    vdata,       saddr      offset13s glc slc
    scratch_store_short_d16_hi                   vaddr,    vdata,       saddr      offset13s glc slc

### MIMG

    INSTRUCTION                DST      SRC0       SRC1     SRC2          MODIFIERS
    ————————————————————————————————————————————————————————————————————————————————————————————————————————
    image_atomic_add                    vdata:dst, vaddr,   srsrc         dmask unorm glc slc a16 lwe da
    image_atomic_and                    vdata:dst, vaddr,   srsrc         dmask unorm glc slc a16 lwe da
    image_atomic_cmpswap                vdata:dst, vaddr,   srsrc         dmask unorm glc slc a16 lwe da
    image_atomic_dec                    vdata:dst, vaddr,   srsrc         dmask unorm glc slc a16 lwe da
    image_atomic_inc                    vdata:dst, vaddr,   srsrc         dmask unorm glc slc a16 lwe da
    image_atomic_or                     vdata:dst, vaddr,   srsrc         dmask unorm glc slc a16 lwe da
    image_atomic_smax                   vdata:dst, vaddr,   srsrc         dmask unorm glc slc a16 lwe da
    image_atomic_smin                   vdata:dst, vaddr,   srsrc         dmask unorm glc slc a16 lwe da
    image_atomic_sub                    vdata:dst, vaddr,   srsrc         dmask unorm glc slc a16 lwe da
    image_atomic_swap                   vdata:dst, vaddr,   srsrc         dmask unorm glc slc a16 lwe da
    image_atomic_umax                   vdata:dst, vaddr,   srsrc         dmask unorm glc slc a16 lwe da
    image_atomic_umin                   vdata:dst, vaddr,   srsrc         dmask unorm glc slc a16 lwe da
    image_atomic_xor                    vdata:dst, vaddr,   srsrc         dmask unorm glc slc a16 lwe da
    image_get_resinfo          vdst,    vaddr,     srsrc                  dmask unorm glc slc a16 lwe da
    image_load                 vdst,    vaddr,     srsrc                  dmask unorm glc slc a16 lwe da d16
    image_load_mip             vdst,    vaddr,     srsrc                  dmask unorm glc slc a16 lwe da d16
    image_load_mip_pck         vdst,    vaddr,     srsrc                  dmask unorm glc slc a16 lwe da
    image_load_mip_pck_sgn     vdst,    vaddr,     srsrc                  dmask unorm glc slc a16 lwe da
    image_load_pck             vdst,    vaddr,     srsrc                  dmask unorm glc slc a16 lwe da
    image_load_pck_sgn         vdst,    vaddr,     srsrc                  dmask unorm glc slc a16 lwe da
    image_sample               vdst,    vaddr,     srsrc,   ssamp         dmask unorm glc slc a16 lwe da d16
    image_store                         vdata,     vaddr,   srsrc         dmask unorm glc slc a16 lwe da d16
    image_store_mip                     vdata,     vaddr,   srsrc         dmask unorm glc slc a16 lwe da d16
    image_store_mip_pck                 vdata,     vaddr,   srsrc         dmask unorm glc slc a16 lwe da
    image_store_pck                     vdata,     vaddr,   srsrc         dmask unorm glc slc a16 lwe da

### MTBUF

    INSTRUCTION                     DST   SRC0   SRC1   SRC2    SRC3      MODIFIERS
    ——————————————————————————————————————————————————————————————————————————————————————————————————————
    tbuffer_load_format_d16_x       vdst, vaddr, srsrc, soffset           fmt idxen offen offset12 glc slc
    tbuffer_load_format_d16_xy      vdst, vaddr, srsrc, soffset           fmt idxen offen offset12 glc slc
    tbuffer_load_format_d16_xyz     vdst, vaddr, srsrc, soffset           fmt idxen offen offset12 glc slc
    tbuffer_load_format_d16_xyzw    vdst, vaddr, srsrc, soffset           fmt idxen offen offset12 glc slc
    tbuffer_load_format_x           vdst, vaddr, srsrc, soffset           fmt idxen offen offset12 glc slc
    tbuffer_load_format_xy          vdst, vaddr, srsrc, soffset           fmt idxen offen offset12 glc slc
    tbuffer_load_format_xyz         vdst, vaddr, srsrc, soffset           fmt idxen offen offset12 glc slc
    tbuffer_load_format_xyzw        vdst, vaddr, srsrc, soffset           fmt idxen offen offset12 glc slc
    tbuffer_store_format_d16_x            vdata, vaddr, srsrc,  soffset   fmt idxen offen offset12 glc slc
    tbuffer_store_format_d16_xy           vdata, vaddr, srsrc,  soffset   fmt idxen offen offset12 glc slc
    tbuffer_store_format_d16_xyz          vdata, vaddr, srsrc,  soffset   fmt idxen offen offset12 glc slc
    tbuffer_store_format_d16_xyzw         vdata, vaddr, srsrc,  soffset   fmt idxen offen offset12 glc slc
    tbuffer_store_format_x                vdata, vaddr, srsrc,  soffset   fmt idxen offen offset12 glc slc
    tbuffer_store_format_xy               vdata, vaddr, srsrc,  soffset   fmt idxen offen offset12 glc slc
    tbuffer_store_format_xyz              vdata, vaddr, srsrc,  soffset   fmt idxen offen offset12 glc slc
    tbuffer_store_format_xyzw             vdata, vaddr, srsrc,  soffset   fmt idxen offen offset12 glc slc

### MUBUF

    INSTRUCTION                   DST       SRC0             SRC1    SRC2    SRC3     MODIFIERS
    ——————————————————————————————————————————————————————————————————————————————————————————————————————————————————
    buffer_atomic_add                       vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_add_f32                   vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_add_f64                   vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_add_x2                    vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_and                       vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_and_x2                    vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_cmpswap                   vdata:dst:b32x2, vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_cmpswap_x2                vdata:dst:b64x2, vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_dec                       vdata:dst:u32,   vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_dec_x2                    vdata:dst:u64,   vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_inc                       vdata:dst:u32,   vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_inc_x2                    vdata:dst:u64,   vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_max_f64                   vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_min_f64                   vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_or                        vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_or_x2                     vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_pk_add_f16                vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_smax                      vdata:dst:i32,   vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_smax_x2                   vdata:dst:i64,   vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_smin                      vdata:dst:i32,   vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_smin_x2                   vdata:dst:i64,   vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_sub                       vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_sub_x2                    vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_swap                      vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_swap_x2                   vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_umax                      vdata:dst:u32,   vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_umax_x2                   vdata:dst:u64,   vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_umin                      vdata:dst:u32,   vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_umin_x2                   vdata:dst:u64,   vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_xor                       vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_xor_x2                    vdata:dst,       vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_invl2
    buffer_load_dword             vdst:opt, vaddr,           srsrc,  soffset          idxen offen offset12 glc slc lds
    buffer_load_dwordx2           vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_dwordx3           vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_dwordx4           vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_format_d16_hi_x   vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_format_d16_x      vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_format_d16_xy     vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_format_d16_xyz    vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_format_d16_xyzw   vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_format_x          vdst:opt, vaddr,           srsrc,  soffset          idxen offen offset12 glc slc lds
    buffer_load_format_xy         vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_format_xyz        vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_format_xyzw       vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_sbyte             vdst:opt, vaddr,           srsrc,  soffset          idxen offen offset12 glc slc lds
    buffer_load_sbyte_d16         vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_sbyte_d16_hi      vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_short_d16         vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_short_d16_hi      vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_sshort            vdst:opt, vaddr,           srsrc,  soffset          idxen offen offset12 glc slc lds
    buffer_load_ubyte             vdst:opt, vaddr,           srsrc,  soffset          idxen offen offset12 glc slc lds
    buffer_load_ubyte_d16         vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_ubyte_d16_hi      vdst,     vaddr,           srsrc,  soffset          idxen offen offset12 glc slc
    buffer_load_ushort            vdst:opt, vaddr,           srsrc,  soffset          idxen offen offset12 glc slc lds
    buffer_store_byte                       vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_byte_d16_hi                vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_dword                      vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_dwordx2                    vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_dwordx3                    vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_dwordx4                    vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_d16_hi_x            vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_d16_x               vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_d16_xy              vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_d16_xyz             vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_d16_xyzw            vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_x                   vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_xy                  vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_xyz                 vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_xyzw                vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_lds_dword                  srsrc,           soffset                  offset12 lds
    buffer_store_short                      vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_short_d16_hi               vdata,           vaddr,  srsrc,  soffset  idxen offen offset12 glc slc
    buffer_wbinvl1
    buffer_wbinvl1_vol
    buffer_wbl2

### SMEM

    INSTRUCTION                    DST       SRC0             SRC1      SRC2           MODIFIERS
    ————————————————————————————————————————————————————————————————————————————————————————————————
    s_atc_probe                              probe,           sbase,    soffset        offset21s
    s_atc_probe_buffer                       probe,           sbase,    soffset        offset20u
    s_atomic_add                             sdata:dst,       sbase,    soffset        offset21s glc
    s_atomic_add_x2                          sdata:dst,       sbase,    soffset        offset21s glc
    s_atomic_and                             sdata:dst,       sbase,    soffset        offset21s glc
    s_atomic_and_x2                          sdata:dst,       sbase,    soffset        offset21s glc
    s_atomic_cmpswap                         sdata:dst:b32x2, sbase,    soffset        offset21s glc
    s_atomic_cmpswap_x2                      sdata:dst:b64x2, sbase,    soffset        offset21s glc
    s_atomic_dec                             sdata:dst:u32,   sbase,    soffset        offset21s glc
    s_atomic_dec_x2                          sdata:dst:u64,   sbase,    soffset        offset21s glc
    s_atomic_inc                             sdata:dst:u32,   sbase,    soffset        offset21s glc
    s_atomic_inc_x2                          sdata:dst:u64,   sbase,    soffset        offset21s glc
    s_atomic_or                              sdata:dst,       sbase,    soffset        offset21s glc
    s_atomic_or_x2                           sdata:dst,       sbase,    soffset        offset21s glc
    s_atomic_smax                            sdata:dst:i32,   sbase,    soffset        offset21s glc
    s_atomic_smax_x2                         sdata:dst:i64,   sbase,    soffset        offset21s glc
    s_atomic_smin                            sdata:dst:i32,   sbase,    soffset        offset21s glc
    s_atomic_smin_x2                         sdata:dst:i64,   sbase,    soffset        offset21s glc
    s_atomic_sub                             sdata:dst,       sbase,    soffset        offset21s glc
    s_atomic_sub_x2                          sdata:dst,       sbase,    soffset        offset21s glc
    s_atomic_swap                            sdata:dst,       sbase,    soffset        offset21s glc
    s_atomic_swap_x2                         sdata:dst,       sbase,    soffset        offset21s glc
    s_atomic_umax                            sdata:dst:u32,   sbase,    soffset        offset21s glc
    s_atomic_umax_x2                         sdata:dst:u64,   sbase,    soffset        offset21s glc
    s_atomic_umin                            sdata:dst:u32,   sbase,    soffset        offset21s glc
    s_atomic_umin_x2                         sdata:dst:u64,   sbase,    soffset        offset21s glc
    s_atomic_xor                             sdata:dst,       sbase,    soffset        offset21s glc
    s_atomic_xor_x2                          sdata:dst,       sbase,    soffset        offset21s glc
    s_buffer_atomic_add                      sdata:dst,       sbase,    soffset        offset20u glc
    s_buffer_atomic_add_x2                   sdata:dst,       sbase,    soffset        offset20u glc
    s_buffer_atomic_and                      sdata:dst,       sbase,    soffset        offset20u glc
    s_buffer_atomic_and_x2                   sdata:dst,       sbase,    soffset        offset20u glc
    s_buffer_atomic_cmpswap                  sdata:dst:b32x2, sbase,    soffset        offset20u glc
    s_buffer_atomic_cmpswap_x2               sdata:dst:b64x2, sbase,    soffset        offset20u glc
    s_buffer_atomic_dec                      sdata:dst:u32,   sbase,    soffset        offset20u glc
    s_buffer_atomic_dec_x2                   sdata:dst:u64,   sbase,    soffset        offset20u glc
    s_buffer_atomic_inc                      sdata:dst:u32,   sbase,    soffset        offset20u glc
    s_buffer_atomic_inc_x2                   sdata:dst:u64,   sbase,    soffset        offset20u glc
    s_buffer_atomic_or                       sdata:dst,       sbase,    soffset        offset20u glc
    s_buffer_atomic_or_x2                    sdata:dst,       sbase,    soffset        offset20u glc
    s_buffer_atomic_smax                     sdata:dst:i32,   sbase,    soffset        offset20u glc
    s_buffer_atomic_smax_x2                  sdata:dst:i64,   sbase,    soffset        offset20u glc
    s_buffer_atomic_smin                     sdata:dst:i32,   sbase,    soffset        offset20u glc
    s_buffer_atomic_smin_x2                  sdata:dst:i64,   sbase,    soffset        offset20u glc
    s_buffer_atomic_sub                      sdata:dst,       sbase,    soffset        offset20u glc
    s_buffer_atomic_sub_x2                   sdata:dst,       sbase,    soffset        offset20u glc
    s_buffer_atomic_swap                     sdata:dst,       sbase,    soffset        offset20u glc
    s_buffer_atomic_swap_x2                  sdata:dst,       sbase,    soffset        offset20u glc
    s_buffer_atomic_umax                     sdata:dst:u32,   sbase,    soffset        offset20u glc
    s_buffer_atomic_umax_x2                  sdata:dst:u64,   sbase,    soffset        offset20u glc
    s_buffer_atomic_umin                     sdata:dst:u32,   sbase,    soffset        offset20u glc
    s_buffer_atomic_umin_x2                  sdata:dst:u64,   sbase,    soffset        offset20u glc
    s_buffer_atomic_xor                      sdata:dst,       sbase,    soffset        offset20u glc
    s_buffer_atomic_xor_x2                   sdata:dst,       sbase,    soffset        offset20u glc
    s_buffer_load_dword            sdst,     sbase,           soffset                  offset20u glc
    s_buffer_load_dwordx16         sdst,     sbase,           soffset                  offset20u glc
    s_buffer_load_dwordx2          sdst,     sbase,           soffset                  offset20u glc
    s_buffer_load_dwordx4          sdst,     sbase,           soffset                  offset20u glc
    s_buffer_load_dwordx8          sdst,     sbase,           soffset                  offset20u glc
    s_buffer_store_dword                     sdata,           sbase,    soffset        offset20u glc
    s_buffer_store_dwordx2                   sdata,           sbase,    soffset        offset20u glc
    s_buffer_store_dwordx4                   sdata,           sbase,    soffset        offset20u glc
    s_dcache_discard                         sbase,           soffset                  offset21s
    s_dcache_discard_x2                      sbase,           soffset                  offset21s
    s_dcache_inv
    s_dcache_inv_vol
    s_dcache_wb
    s_dcache_wb_vol
    s_load_dword                   sdst,     sbase,           soffset                  offset21s glc
    s_load_dwordx16                sdst,     sbase,           soffset                  offset21s glc
    s_load_dwordx2                 sdst,     sbase,           soffset                  offset21s glc
    s_load_dwordx4                 sdst,     sbase,           soffset                  offset21s glc
    s_load_dwordx8                 sdst,     sbase,           soffset                  offset21s glc
    s_memrealtime                  sdst:b64
    s_memtime                      sdst:b64
    s_scratch_load_dword           sdst,     sbase,           soffset                  offset21s glc
    s_scratch_load_dwordx2         sdst,     sbase,           soffset                  offset21s glc
    s_scratch_load_dwordx4         sdst,     sbase,           soffset                  offset21s glc
    s_scratch_store_dword                    sdata,           sbase,    soffset        offset21s glc
    s_scratch_store_dwordx2                  sdata,           sbase,    soffset        offset21s glc
    s_scratch_store_dwordx4                  sdata,           sbase,    soffset        offset21s glc
    s_store_dword                            sdata,           sbase,    soffset        offset21s glc
    s_store_dwordx2                          sdata,           sbase,    soffset        offset21s glc
    s_store_dwordx4                          sdata,           sbase,    soffset        offset21s glc

### SOP1

    INSTRUCTION                    DST       SRC
    ———————————————————————————————————————————————————
    s_abs_i32                      sdst,     ssrc
    s_and_saveexec_b64             sdst,     ssrc
    s_andn1_saveexec_b64           sdst,     ssrc
    s_andn1_wrexec_b64             sdst,     ssrc
    s_andn2_saveexec_b64           sdst,     ssrc
    s_andn2_wrexec_b64             sdst,     ssrc
    s_bcnt0_i32_b32                sdst,     ssrc
    s_bcnt0_i32_b64                sdst,     ssrc
    s_bcnt1_i32_b32                sdst,     ssrc
    s_bcnt1_i32_b64                sdst,     ssrc
    s_bitreplicate_b64_b32         sdst,     ssrc
    s_bitset0_b32                  sdst,     ssrc
    s_bitset0_b64                  sdst,     ssrc:b32
    s_bitset1_b32                  sdst,     ssrc
    s_bitset1_b64                  sdst,     ssrc:b32
    s_brev_b32                     sdst,     ssrc
    s_brev_b64                     sdst,     ssrc
    s_cbranch_join                           ssrc
    s_cmov_b32                     sdst,     ssrc
    s_cmov_b64                     sdst,     ssrc
    s_ff0_i32_b32                  sdst,     ssrc
    s_ff0_i32_b64                  sdst,     ssrc
    s_ff1_i32_b32                  sdst,     ssrc
    s_ff1_i32_b64                  sdst,     ssrc
    s_flbit_i32                    sdst,     ssrc
    s_flbit_i32_b32                sdst,     ssrc
    s_flbit_i32_b64                sdst,     ssrc
    s_flbit_i32_i64                sdst,     ssrc
    s_getpc_b64                    sdst
    s_mov_b32                      sdst,     ssrc
    s_mov_b64                      sdst,     ssrc
    s_movreld_b32                  sdst,     ssrc
    s_movreld_b64                  sdst,     ssrc
    s_movrels_b32                  sdst,     ssrc
    s_movrels_b64                  sdst,     ssrc
    s_nand_saveexec_b64            sdst,     ssrc
    s_nor_saveexec_b64             sdst,     ssrc
    s_not_b32                      sdst,     ssrc
    s_not_b64                      sdst,     ssrc
    s_or_saveexec_b64              sdst,     ssrc
    s_orn1_saveexec_b64            sdst,     ssrc
    s_orn2_saveexec_b64            sdst,     ssrc
    s_quadmask_b32                 sdst,     ssrc
    s_quadmask_b64                 sdst,     ssrc
    s_rfe_b64                                ssrc
    s_set_gpr_idx_idx                        ssrc
    s_setpc_b64                              ssrc
    s_sext_i32_i16                 sdst,     ssrc
    s_sext_i32_i8                  sdst,     ssrc
    s_swappc_b64                   sdst,     ssrc
    s_wqm_b32                      sdst,     ssrc
    s_wqm_b64                      sdst,     ssrc
    s_xnor_saveexec_b64            sdst,     ssrc
    s_xor_saveexec_b64             sdst,     ssrc

### SOP2

    INSTRUCTION                    DST       SRC0       SRC1
    ——————————————————————————————————————————————————————————————
    s_absdiff_i32                  sdst,     ssrc0,     ssrc1
    s_add_i32                      sdst,     ssrc0,     ssrc1
    s_add_u32                      sdst,     ssrc0,     ssrc1
    s_addc_u32                     sdst,     ssrc0,     ssrc1
    s_and_b32                      sdst,     ssrc0,     ssrc1
    s_and_b64                      sdst,     ssrc0,     ssrc1
    s_andn2_b32                    sdst,     ssrc0,     ssrc1
    s_andn2_b64                    sdst,     ssrc0,     ssrc1
    s_ashr_i32                     sdst,     ssrc0,     ssrc1:u32
    s_ashr_i64                     sdst,     ssrc0,     ssrc1:u32
    s_bfe_i32                      sdst,     ssrc0,     ssrc1:u32
    s_bfe_i64                      sdst,     ssrc0,     ssrc1:u32
    s_bfe_u32                      sdst,     ssrc0,     ssrc1
    s_bfe_u64                      sdst,     ssrc0,     ssrc1:u32
    s_bfm_b32                      sdst,     ssrc0,     ssrc1
    s_bfm_b64                      sdst,     ssrc0:b32, ssrc1:b32
    s_cbranch_g_fork                         ssrc0,     ssrc1
    s_cselect_b32                  sdst,     ssrc0,     ssrc1
    s_cselect_b64                  sdst,     ssrc0,     ssrc1
    s_lshl1_add_u32                sdst,     ssrc0,     ssrc1
    s_lshl2_add_u32                sdst,     ssrc0,     ssrc1
    s_lshl3_add_u32                sdst,     ssrc0,     ssrc1
    s_lshl4_add_u32                sdst,     ssrc0,     ssrc1
    s_lshl_b32                     sdst,     ssrc0,     ssrc1:u32
    s_lshl_b64                     sdst,     ssrc0,     ssrc1:u32
    s_lshr_b32                     sdst,     ssrc0,     ssrc1:u32
    s_lshr_b64                     sdst,     ssrc0,     ssrc1:u32
    s_max_i32                      sdst,     ssrc0,     ssrc1
    s_max_u32                      sdst,     ssrc0,     ssrc1
    s_min_i32                      sdst,     ssrc0,     ssrc1
    s_min_u32                      sdst,     ssrc0,     ssrc1
    s_mul_hi_i32                   sdst,     ssrc0,     ssrc1
    s_mul_hi_u32                   sdst,     ssrc0,     ssrc1
    s_mul_i32                      sdst,     ssrc0,     ssrc1
    s_nand_b32                     sdst,     ssrc0,     ssrc1
    s_nand_b64                     sdst,     ssrc0,     ssrc1
    s_nor_b32                      sdst,     ssrc0,     ssrc1
    s_nor_b64                      sdst,     ssrc0,     ssrc1
    s_or_b32                       sdst,     ssrc0,     ssrc1
    s_or_b64                       sdst,     ssrc0,     ssrc1
    s_orn2_b32                     sdst,     ssrc0,     ssrc1
    s_orn2_b64                     sdst,     ssrc0,     ssrc1
    s_pack_hh_b32_b16              sdst,     ssrc0:b32, ssrc1:b32
    s_pack_lh_b32_b16              sdst,     ssrc0,     ssrc1:b32
    s_pack_ll_b32_b16              sdst,     ssrc0,     ssrc1
    s_rfe_restore_b64                        ssrc0,     ssrc1:b32
    s_sub_i32                      sdst,     ssrc0,     ssrc1
    s_sub_u32                      sdst,     ssrc0,     ssrc1
    s_subb_u32                     sdst,     ssrc0,     ssrc1
    s_xnor_b32                     sdst,     ssrc0,     ssrc1
    s_xnor_b64                     sdst,     ssrc0,     ssrc1
    s_xor_b32                      sdst,     ssrc0,     ssrc1
    s_xor_b64                      sdst,     ssrc0,     ssrc1

### SOPC

    INSTRUCTION                    SRC0      SRC1
    ———————————————————————————————————————————————————
    s_bitcmp0_b32                  ssrc0,    ssrc1
    s_bitcmp0_b64                  ssrc0,    ssrc1:u32
    s_bitcmp1_b32                  ssrc0,    ssrc1
    s_bitcmp1_b64                  ssrc0,    ssrc1:u32
    s_cmp_eq_i32                   ssrc0,    ssrc1
    s_cmp_eq_u32                   ssrc0,    ssrc1
    s_cmp_eq_u64                   ssrc0,    ssrc1
    s_cmp_ge_i32                   ssrc0,    ssrc1
    s_cmp_ge_u32                   ssrc0,    ssrc1
    s_cmp_gt_i32                   ssrc0,    ssrc1
    s_cmp_gt_u32                   ssrc0,    ssrc1
    s_cmp_le_i32                   ssrc0,    ssrc1
    s_cmp_le_u32                   ssrc0,    ssrc1
    s_cmp_lg_i32                   ssrc0,    ssrc1
    s_cmp_lg_u32                   ssrc0,    ssrc1
    s_cmp_lg_u64                   ssrc0,    ssrc1
    s_cmp_lt_i32                   ssrc0,    ssrc1
    s_cmp_lt_u32                   ssrc0,    ssrc1
    s_set_gpr_idx_on               ssrc,     imask
    s_setvskip                     ssrc0,    ssrc1

### SOPK

    INSTRUCTION                    DST       SRC0      SRC1
    —————————————————————————————————————————————————————————————
    s_addk_i32                     sdst,     imm16
    s_call_b64                     sdst,     label
    s_cbranch_i_fork                         ssrc,     label
    s_cmovk_i32                    sdst,     imm16
    s_cmpk_eq_i32                            ssrc,     imm16
    s_cmpk_eq_u32                            ssrc,     imm16
    s_cmpk_ge_i32                            ssrc,     imm16
    s_cmpk_ge_u32                            ssrc,     imm16
    s_cmpk_gt_i32                            ssrc,     imm16
    s_cmpk_gt_u32                            ssrc,     imm16
    s_cmpk_le_i32                            ssrc,     imm16
    s_cmpk_le_u32                            ssrc,     imm16
    s_cmpk_lg_i32                            ssrc,     imm16
    s_cmpk_lg_u32                            ssrc,     imm16
    s_cmpk_lt_i32                            ssrc,     imm16
    s_cmpk_lt_u32                            ssrc,     imm16
    s_getreg_b32                   sdst,     hwreg
    s_movk_i32                     sdst,     imm16
    s_mulk_i32                     sdst,     imm16
    s_setreg_b32                   hwreg,    ssrc
    s_setreg_imm32_b32             hwreg,    simm32

### SOPP

    INSTRUCTION                    SRC
    —————————————————————————————————————————
    s_barrier
    s_branch                       label
    s_cbranch_cdbgsys              label
    s_cbranch_cdbgsys_and_user     label
    s_cbranch_cdbgsys_or_user      label
    s_cbranch_cdbguser             label
    s_cbranch_execnz               label
    s_cbranch_execz                label
    s_cbranch_scc0                 label
    s_cbranch_scc1                 label
    s_cbranch_vccnz                label
    s_cbranch_vccz                 label
    s_decperflevel                 imm16
    s_endpgm
    s_endpgm_ordered_ps_done
    s_endpgm_saved
    s_icache_inv
    s_incperflevel                 imm16
    s_nop                          imm16
    s_sendmsg                      msg
    s_sendmsghalt                  msg
    s_set_gpr_idx_mode             imask
    s_set_gpr_idx_off
    s_sethalt                      imm16
    s_setkill                      imm16
    s_setprio                      imm16
    s_sleep                        imm16
    s_trap                         imm16
    s_ttracedata
    s_waitcnt                      waitcnt
    s_wakeup

### VOP1

    INSTRUCTION                         DST        SRC            MODIFIERS
    ——————————————————————————————————————————————————————————————————————————————————————————————————————
    v_accvgpr_mov_b32                   vdst,      vsrc
    v_bfrev_b32                         vdst,      src
    v_bfrev_b32_dpp                     vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_bfrev_b32_sdwa                    vdst,      src:m          dst_sel dst_unused src0_sel
    v_ceil_f16                          vdst,      src
    v_ceil_f16_dpp                      vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_ceil_f16_sdwa                     vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_ceil_f32                          vdst,      src
    v_ceil_f32_dpp                      vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_ceil_f32_sdwa                     vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_ceil_f64                          vdst,      src
    v_ceil_f64_dpp                      vdst,      vsrc:m         dpp64_ctrl row_mask bank_mask bound_ctrl
    v_clrexcp
    v_cos_f16                           vdst,      src
    v_cos_f16_dpp                       vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cos_f16_sdwa                      vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_cos_f32                           vdst,      src
    v_cos_f32_dpp                       vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cos_f32_sdwa                      vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_cvt_f16_f32                       vdst,      src
    v_cvt_f16_f32_dpp                   vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_f16_f32_sdwa                  vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_cvt_f16_i16                       vdst,      src
    v_cvt_f16_i16_dpp                   vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_f16_i16_sdwa                  vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_cvt_f16_u16                       vdst,      src
    v_cvt_f16_u16_dpp                   vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_f16_u16_sdwa                  vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_cvt_f32_f16                       vdst,      src
    v_cvt_f32_f16_dpp                   vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_f32_f16_sdwa                  vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_cvt_f32_f64                       vdst,      src
    v_cvt_f32_f64_dpp                   vdst,      vsrc:m         dpp64_ctrl row_mask bank_mask bound_ctrl
    v_cvt_f32_i32                       vdst,      src
    v_cvt_f32_i32_dpp                   vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_f32_i32_sdwa                  vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_cvt_f32_u32                       vdst,      src
    v_cvt_f32_u32_dpp                   vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_f32_u32_sdwa                  vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_cvt_f32_ubyte0                    vdst,      src
    v_cvt_f32_ubyte0_dpp                vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_f32_ubyte0_sdwa               vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_cvt_f32_ubyte1                    vdst,      src
    v_cvt_f32_ubyte1_dpp                vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_f32_ubyte1_sdwa               vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_cvt_f32_ubyte2                    vdst,      src
    v_cvt_f32_ubyte2_dpp                vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_f32_ubyte2_sdwa               vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_cvt_f32_ubyte3                    vdst,      src
    v_cvt_f32_ubyte3_dpp                vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_f32_ubyte3_sdwa               vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_cvt_f64_f32                       vdst,      src
    v_cvt_f64_i32                       vdst,      src
    v_cvt_f64_u32                       vdst,      src
    v_cvt_flr_i32_f32                   vdst,      src
    v_cvt_flr_i32_f32_dpp               vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_flr_i32_f32_sdwa              vdst,      src:m          dst_sel dst_unused src0_sel
    v_cvt_i16_f16                       vdst,      src
    v_cvt_i16_f16_dpp                   vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_i16_f16_sdwa                  vdst,      src:m          clamp dst_sel dst_unused src0_sel
    v_cvt_i32_f32                       vdst,      src
    v_cvt_i32_f32_dpp                   vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_i32_f32_sdwa                  vdst,      src:m          clamp dst_sel dst_unused src0_sel
    v_cvt_i32_f64                       vdst,      src
    v_cvt_i32_f64_dpp                   vdst,      vsrc:m         dpp64_ctrl row_mask bank_mask bound_ctrl
    v_cvt_norm_i16_f16                  vdst,      src
    v_cvt_norm_i16_f16_dpp              vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_norm_i16_f16_sdwa             vdst,      src:m          clamp dst_sel dst_unused src0_sel
    v_cvt_norm_u16_f16                  vdst,      src
    v_cvt_norm_u16_f16_dpp              vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_norm_u16_f16_sdwa             vdst,      src:m          clamp dst_sel dst_unused src0_sel
    v_cvt_off_f32_i4                    vdst,      src
    v_cvt_off_f32_i4_dpp                vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_off_f32_i4_sdwa               vdst,      src            clamp omod dst_sel dst_unused src0_sel
    v_cvt_rpi_i32_f32                   vdst,      src
    v_cvt_rpi_i32_f32_dpp               vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_rpi_i32_f32_sdwa              vdst,      src:m          dst_sel dst_unused src0_sel
    v_cvt_u16_f16                       vdst,      src
    v_cvt_u16_f16_dpp                   vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_u16_f16_sdwa                  vdst,      src:m          clamp dst_sel dst_unused src0_sel
    v_cvt_u32_f32                       vdst,      src
    v_cvt_u32_f32_dpp                   vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cvt_u32_f32_sdwa                  vdst,      src:m          clamp dst_sel dst_unused src0_sel
    v_cvt_u32_f64                       vdst,      src
    v_cvt_u32_f64_dpp                   vdst,      vsrc:m         dpp64_ctrl row_mask bank_mask bound_ctrl
    v_exp_f16                           vdst,      src
    v_exp_f16_dpp                       vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_exp_f16_sdwa                      vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_exp_f32                           vdst,      src
    v_exp_f32_dpp                       vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_exp_f32_sdwa                      vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_exp_legacy_f32                    vdst,      src
    v_exp_legacy_f32_dpp                vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_exp_legacy_f32_sdwa               vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_ffbh_i32                          vdst,      src
    v_ffbh_i32_dpp                      vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_ffbh_i32_sdwa                     vdst,      src:m          dst_sel dst_unused src0_sel
    v_ffbh_u32                          vdst,      src
    v_ffbh_u32_dpp                      vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_ffbh_u32_sdwa                     vdst,      src:m          dst_sel dst_unused src0_sel
    v_ffbl_b32                          vdst,      src
    v_ffbl_b32_dpp                      vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_ffbl_b32_sdwa                     vdst,      src:m          dst_sel dst_unused src0_sel
    v_floor_f16                         vdst,      src
    v_floor_f16_dpp                     vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_floor_f16_sdwa                    vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_floor_f32                         vdst,      src
    v_floor_f32_dpp                     vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_floor_f32_sdwa                    vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_floor_f64                         vdst,      src
    v_floor_f64_dpp                     vdst,      vsrc:m         dpp64_ctrl row_mask bank_mask bound_ctrl
    v_fract_f16                         vdst,      src
    v_fract_f16_dpp                     vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_fract_f16_sdwa                    vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_fract_f32                         vdst,      src
    v_fract_f32_dpp                     vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_fract_f32_sdwa                    vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_fract_f64                         vdst,      src
    v_fract_f64_dpp                     vdst,      vsrc:m         dpp64_ctrl row_mask bank_mask bound_ctrl
    v_frexp_exp_i16_f16                 vdst,      src
    v_frexp_exp_i16_f16_dpp             vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_frexp_exp_i16_f16_sdwa            vdst,      src:m          dst_sel dst_unused src0_sel
    v_frexp_exp_i32_f32                 vdst,      src
    v_frexp_exp_i32_f32_dpp             vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_frexp_exp_i32_f32_sdwa            vdst,      src:m          dst_sel dst_unused src0_sel
    v_frexp_exp_i32_f64                 vdst,      src
    v_frexp_exp_i32_f64_dpp             vdst,      vsrc:m         dpp64_ctrl row_mask bank_mask bound_ctrl
    v_frexp_mant_f16                    vdst,      src
    v_frexp_mant_f16_dpp                vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_frexp_mant_f16_sdwa               vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_frexp_mant_f32                    vdst,      src
    v_frexp_mant_f32_dpp                vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_frexp_mant_f32_sdwa               vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_frexp_mant_f64                    vdst,      src
    v_frexp_mant_f64_dpp                vdst,      vsrc:m         dpp64_ctrl row_mask bank_mask bound_ctrl
    v_log_f16                           vdst,      src
    v_log_f16_dpp                       vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_log_f16_sdwa                      vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_log_f32                           vdst,      src
    v_log_f32_dpp                       vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_log_f32_sdwa                      vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_log_legacy_f32                    vdst,      src
    v_log_legacy_f32_dpp                vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_log_legacy_f32_sdwa               vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_mov_b32                           vdst,      src
    v_mov_b32_dpp                       vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_mov_b32_sdwa                      vdst,      src            dst_sel dst_unused src0_sel
    v_nop
    v_not_b32                           vdst,      src
    v_not_b32_dpp                       vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_not_b32_sdwa                      vdst,      src:m          dst_sel dst_unused src0_sel
    v_rcp_f16                           vdst,      src
    v_rcp_f16_dpp                       vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_rcp_f16_sdwa                      vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_rcp_f32                           vdst,      src
    v_rcp_f32_dpp                       vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_rcp_f32_sdwa                      vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_rcp_f64                           vdst,      src
    v_rcp_iflag_f32                     vdst,      src
    v_rcp_iflag_f32_dpp                 vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_rcp_iflag_f32_sdwa                vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_readfirstlane_b32                 sdst,      vsrc
    v_rndne_f16                         vdst,      src
    v_rndne_f16_dpp                     vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_rndne_f16_sdwa                    vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_rndne_f32                         vdst,      src
    v_rndne_f32_dpp                     vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_rndne_f32_sdwa                    vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_rndne_f64                         vdst,      src
    v_rsq_f16                           vdst,      src
    v_rsq_f16_dpp                       vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_rsq_f16_sdwa                      vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_rsq_f32                           vdst,      src
    v_rsq_f32_dpp                       vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_rsq_f32_sdwa                      vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_rsq_f64                           vdst,      src
    v_sat_pk_u8_i16                     vdst:u8x4, src
    v_sat_pk_u8_i16_dpp                 vdst:u8x4, vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_sat_pk_u8_i16_sdwa                vdst:u8x4, src:m          dst_sel dst_unused src0_sel
    v_screen_partition_4se_b32          vdst,      src
    v_screen_partition_4se_b32_dpp      vdst,      vsrc           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_screen_partition_4se_b32_sdwa     vdst,      src:m          dst_sel dst_unused src0_sel
    v_sin_f16                           vdst,      src
    v_sin_f16_dpp                       vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_sin_f16_sdwa                      vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_sin_f32                           vdst,      src
    v_sin_f32_dpp                       vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_sin_f32_sdwa                      vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_sqrt_f16                          vdst,      src
    v_sqrt_f16_dpp                      vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_sqrt_f16_sdwa                     vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_sqrt_f32                          vdst,      src
    v_sqrt_f32_dpp                      vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_sqrt_f32_sdwa                     vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_sqrt_f64                          vdst,      src
    v_swap_b32                          vdst,      vsrc
    v_trunc_f16                         vdst,      src
    v_trunc_f16_dpp                     vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_trunc_f16_sdwa                    vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_trunc_f32                         vdst,      src
    v_trunc_f32_dpp                     vdst,      vsrc:m         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_trunc_f32_sdwa                    vdst,      src:m          clamp omod dst_sel dst_unused src0_sel
    v_trunc_f64                         vdst,      src
    v_trunc_f64_dpp                     vdst,      vsrc:m         dpp64_ctrl row_mask bank_mask bound_ctrl

### VOP2

    INSTRUCTION            DST0  DST1 SRC0           SRC1          SRC2    MODIFIERS
    ——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
    v_add_co_u32           vdst, vcc, src0,          vsrc1
    v_add_co_u32_dpp       vdst, vcc, vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_add_co_u32_sdwa      vdst, vcc, src0:m,        src1:m                clamp dst_sel dst_unused src0_sel src1_sel
    v_add_f16              vdst,      src0,          vsrc1
    v_add_f16_dpp          vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_add_f16_sdwa         vdst,      src0:m,        src1:m                clamp omod dst_sel dst_unused src0_sel src1_sel
    v_add_f32              vdst,      src0,          vsrc1
    v_add_f32_dpp          vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_add_f32_sdwa         vdst,      src0:m,        src1:m                clamp omod dst_sel dst_unused src0_sel src1_sel
    v_add_u16              vdst,      src0,          vsrc1
    v_add_u16_dpp          vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_add_u16_sdwa         vdst,      src0:m,        src1:m                clamp dst_sel dst_unused src0_sel src1_sel
    v_add_u32              vdst,      src0,          vsrc1
    v_add_u32_dpp          vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_add_u32_sdwa         vdst,      src0:m,        src1:m                clamp dst_sel dst_unused src0_sel src1_sel
    v_addc_co_u32          vdst, vcc, src0,          vsrc1,        vcc
    v_addc_co_u32_dpp      vdst, vcc, vsrc0,         vsrc1,        vcc     dpp32_ctrl row_mask bank_mask bound_ctrl
    v_addc_co_u32_sdwa     vdst, vcc, src0:m,        src1:m,       vcc     clamp dst_sel dst_unused src0_sel src1_sel
    v_and_b32              vdst,      src0,          vsrc1
    v_and_b32_dpp          vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_and_b32_sdwa         vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel
    v_ashrrev_i16          vdst,      src0:u16,      vsrc1
    v_ashrrev_i16_dpp      vdst,      vsrc0:u16,     vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_ashrrev_i16_sdwa     vdst,      src0:m:u16,    src1:m                dst_sel dst_unused src0_sel src1_sel
    v_ashrrev_i32          vdst,      src0:u32,      vsrc1
    v_ashrrev_i32_dpp      vdst,      vsrc0:u32,     vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_ashrrev_i32_sdwa     vdst,      src0:m:u32,    src1:m                dst_sel dst_unused src0_sel src1_sel
    v_cndmask_b32          vdst,      src0,          vsrc1,        vcc
    v_cndmask_b32_dpp      vdst,      vsrc0:m,       vsrc1:m,      vcc     dpp32_ctrl row_mask bank_mask bound_ctrl
    v_cndmask_b32_sdwa     vdst,      src0:m,        src1:m,       vcc     dst_sel dst_unused src0_sel src1_sel
    v_dot2c_f32_f16        vdst,      src0:f16x2,    vsrc1:f16x2
    v_dot2c_f32_f16_dpp    vdst,      vsrc0:m:f16x2, vsrc1:m:f16x2         dpp32_ctrl row_mask bank_mask bound_ctrl
    v_dot2c_i32_i16        vdst,      src0:i16x2,    vsrc1:i16x2
    v_dot2c_i32_i16_dpp    vdst,      vsrc0:i16x2,   vsrc1:i16x2           dpp32_ctrl row_mask bank_mask bound_ctrl
    v_dot4c_i32_i8         vdst,      src0:i8x4,     vsrc1:i8x4
    v_dot4c_i32_i8_dpp     vdst,      vsrc0:i8x4,    vsrc1:i8x4            dpp32_ctrl row_mask bank_mask bound_ctrl
    v_dot8c_i32_i4         vdst,      src0:i4x8,     vsrc1:i4x8
    v_dot8c_i32_i4_dpp     vdst,      vsrc0:i4x8,    vsrc1:i4x8            dpp32_ctrl row_mask bank_mask bound_ctrl
    v_fmac_f32             vdst,      src0,          vsrc1
    v_fmac_f32_dpp         vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_fmac_f64             vdst,      src0,          vsrc1
    v_fmac_f64_dpp         vdst,      vsrc0:m,       vsrc1:m               dpp64_ctrl row_mask bank_mask bound_ctrl
    v_ldexp_f16            vdst,      src0,          vsrc1:i16
    v_ldexp_f16_dpp        vdst,      vsrc0:m,       vsrc1:i16             dpp32_ctrl row_mask bank_mask bound_ctrl
    v_ldexp_f16_sdwa       vdst,      src0:m,        src1:m:i16            clamp omod dst_sel dst_unused src0_sel src1_sel
    v_lshlrev_b16          vdst,      src0:u16,      vsrc1
    v_lshlrev_b16_dpp      vdst,      vsrc0:u16,     vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_lshlrev_b16_sdwa     vdst,      src0:m:u16,    src1:m                dst_sel dst_unused src0_sel src1_sel
    v_lshlrev_b32          vdst,      src0:u32,      vsrc1
    v_lshlrev_b32_dpp      vdst,      vsrc0:u32,     vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_lshlrev_b32_sdwa     vdst,      src0:m:u32,    src1:m                dst_sel dst_unused src0_sel src1_sel
    v_lshrrev_b16          vdst,      src0:u16,      vsrc1
    v_lshrrev_b16_dpp      vdst,      vsrc0:u16,     vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_lshrrev_b16_sdwa     vdst,      src0:m:u16,    src1:m                dst_sel dst_unused src0_sel src1_sel
    v_lshrrev_b32          vdst,      src0:u32,      vsrc1
    v_lshrrev_b32_dpp      vdst,      vsrc0:u32,     vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_lshrrev_b32_sdwa     vdst,      src0:m:u32,    src1:m                dst_sel dst_unused src0_sel src1_sel
    v_mac_f16              vdst,      src0,          vsrc1
    v_mac_f16_dpp          vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_mac_f32              vdst,      src0,          vsrc1
    v_mac_f32_dpp          vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_madak_f16            vdst,      src0,          vsrc1,        simm32
    v_madak_f32            vdst,      src0,          vsrc1,        simm32
    v_madmk_f16            vdst,      src0,          simm32,       vsrc2
    v_madmk_f32            vdst,      src0,          simm32,       vsrc2
    v_max_f16              vdst,      src0,          vsrc1
    v_max_f16_dpp          vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_max_f16_sdwa         vdst,      src0:m,        src1:m                clamp omod dst_sel dst_unused src0_sel src1_sel
    v_max_f32              vdst,      src0,          vsrc1
    v_max_f32_dpp          vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_max_f32_sdwa         vdst,      src0:m,        src1:m                clamp omod dst_sel dst_unused src0_sel src1_sel
    v_max_i16              vdst,      src0,          vsrc1
    v_max_i16_dpp          vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_max_i16_sdwa         vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel
    v_max_i32              vdst,      src0,          vsrc1
    v_max_i32_dpp          vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_max_i32_sdwa         vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel
    v_max_u16              vdst,      src0,          vsrc1
    v_max_u16_dpp          vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_max_u16_sdwa         vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel
    v_max_u32              vdst,      src0,          vsrc1
    v_max_u32_dpp          vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_max_u32_sdwa         vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel
    v_min_f16              vdst,      src0,          vsrc1
    v_min_f16_dpp          vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_min_f16_sdwa         vdst,      src0:m,        src1:m                clamp omod dst_sel dst_unused src0_sel src1_sel
    v_min_f32              vdst,      src0,          vsrc1
    v_min_f32_dpp          vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_min_f32_sdwa         vdst,      src0:m,        src1:m                clamp omod dst_sel dst_unused src0_sel src1_sel
    v_min_i16              vdst,      src0,          vsrc1
    v_min_i16_dpp          vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_min_i16_sdwa         vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel
    v_min_i32              vdst,      src0,          vsrc1
    v_min_i32_dpp          vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_min_i32_sdwa         vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel
    v_min_u16              vdst,      src0,          vsrc1
    v_min_u16_dpp          vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_min_u16_sdwa         vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel
    v_min_u32              vdst,      src0,          vsrc1
    v_min_u32_dpp          vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_min_u32_sdwa         vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel
    v_mul_f16              vdst,      src0,          vsrc1
    v_mul_f16_dpp          vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_mul_f16_sdwa         vdst,      src0:m,        src1:m                clamp omod dst_sel dst_unused src0_sel src1_sel
    v_mul_f32              vdst,      src0,          vsrc1
    v_mul_f32_dpp          vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_mul_f32_sdwa         vdst,      src0:m,        src1:m                clamp omod dst_sel dst_unused src0_sel src1_sel
    v_mul_hi_i32_i24       vdst,      src0,          vsrc1
    v_mul_hi_i32_i24_dpp   vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_mul_hi_i32_i24_sdwa  vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel
    v_mul_hi_u32_u24       vdst,      src0,          vsrc1
    v_mul_hi_u32_u24_dpp   vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_mul_hi_u32_u24_sdwa  vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel
    v_mul_i32_i24          vdst,      src0,          vsrc1
    v_mul_i32_i24_dpp      vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_mul_i32_i24_sdwa     vdst,      src0:m,        src1:m                clamp dst_sel dst_unused src0_sel src1_sel
    v_mul_lo_u16           vdst,      src0,          vsrc1
    v_mul_lo_u16_dpp       vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_mul_lo_u16_sdwa      vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel
    v_mul_u32_u24          vdst,      src0,          vsrc1
    v_mul_u32_u24_dpp      vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_mul_u32_u24_sdwa     vdst,      src0:m,        src1:m                clamp dst_sel dst_unused src0_sel src1_sel
    v_or_b32               vdst,      src0,          vsrc1
    v_or_b32_dpp           vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_or_b32_sdwa          vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel
    v_pk_fmac_f16          vdst,      src0,          vsrc1
    v_sub_co_u32           vdst, vcc, src0,          vsrc1
    v_sub_co_u32_dpp       vdst, vcc, vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_sub_co_u32_sdwa      vdst, vcc, src0:m,        src1:m                clamp dst_sel dst_unused src0_sel src1_sel
    v_sub_f16              vdst,      src0,          vsrc1
    v_sub_f16_dpp          vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_sub_f16_sdwa         vdst,      src0:m,        src1:m                clamp omod dst_sel dst_unused src0_sel src1_sel
    v_sub_f32              vdst,      src0,          vsrc1
    v_sub_f32_dpp          vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_sub_f32_sdwa         vdst,      src0:m,        src1:m                clamp omod dst_sel dst_unused src0_sel src1_sel
    v_sub_u16              vdst,      src0,          vsrc1
    v_sub_u16_dpp          vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_sub_u16_sdwa         vdst,      src0:m,        src1:m                clamp dst_sel dst_unused src0_sel src1_sel
    v_sub_u32              vdst,      src0,          vsrc1
    v_sub_u32_dpp          vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_sub_u32_sdwa         vdst,      src0:m,        src1:m                clamp dst_sel dst_unused src0_sel src1_sel
    v_subb_co_u32          vdst, vcc, src0,          vsrc1,        vcc
    v_subb_co_u32_dpp      vdst, vcc, vsrc0,         vsrc1,        vcc     dpp32_ctrl row_mask bank_mask bound_ctrl
    v_subb_co_u32_sdwa     vdst, vcc, src0:m,        src1:m,       vcc     clamp dst_sel dst_unused src0_sel src1_sel
    v_subbrev_co_u32       vdst, vcc, src0,          vsrc1,        vcc
    v_subbrev_co_u32_dpp   vdst, vcc, vsrc0,         vsrc1,        vcc     dpp32_ctrl row_mask bank_mask bound_ctrl
    v_subbrev_co_u32_sdwa  vdst, vcc, src0:m,        src1:m,       vcc     clamp dst_sel dst_unused src0_sel src1_sel
    v_subrev_co_u32        vdst, vcc, src0,          vsrc1
    v_subrev_co_u32_dpp    vdst, vcc, vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_subrev_co_u32_sdwa   vdst, vcc, src0:m,        src1:m                clamp dst_sel dst_unused src0_sel src1_sel
    v_subrev_f16           vdst,      src0,          vsrc1
    v_subrev_f16_dpp       vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_subrev_f16_sdwa      vdst,      src0:m,        src1:m                clamp omod dst_sel dst_unused src0_sel src1_sel
    v_subrev_f32           vdst,      src0,          vsrc1
    v_subrev_f32_dpp       vdst,      vsrc0:m,       vsrc1:m               dpp32_ctrl row_mask bank_mask bound_ctrl
    v_subrev_f32_sdwa      vdst,      src0:m,        src1:m                clamp omod dst_sel dst_unused src0_sel src1_sel
    v_subrev_u16           vdst,      src0,          vsrc1
    v_subrev_u16_dpp       vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_subrev_u16_sdwa      vdst,      src0:m,        src1:m                clamp dst_sel dst_unused src0_sel src1_sel
    v_subrev_u32           vdst,      src0,          vsrc1
    v_subrev_u32_dpp       vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_subrev_u32_sdwa      vdst,      src0:m,        src1:m                clamp dst_sel dst_unused src0_sel src1_sel
    v_xnor_b32             vdst,      src0,          vsrc1
    v_xnor_b32_dpp         vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_xnor_b32_sdwa        vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel
    v_xor_b32              vdst,      src0,          vsrc1
    v_xor_b32_dpp          vdst,      vsrc0,         vsrc1                 dpp32_ctrl row_mask bank_mask bound_ctrl
    v_xor_b32_sdwa         vdst,      src0:m,        src1:m                dst_sel dst_unused src0_sel src1_sel

### VOP3

    INSTRUCTION                     DST0        DST1  SRC0          SRC1         SRC2         MODIFIERS
    ———————————————————————————————————————————————————————————————————————————————————————————————————————————
    v_add3_u32                      vdst,             src0,         src1,        src2
    v_add_co_u32_e64                vdst,       sdst, src0,         src1                      clamp
    v_add_f16_e64                   vdst,             src0:m,       src1:m                    clamp omod
    v_add_f32_e64                   vdst,             src0:m,       src1:m                    clamp omod
    v_add_f64                       vdst,             src0:m,       src1:m                    clamp omod
    v_add_i16                       vdst,             src0,         src1                      op_sel clamp
    v_add_i32                       vdst,             src0,         src1                      clamp
    v_add_lshl_u32                  vdst,             src0,         src1,        src2
    v_add_u16_e64                   vdst,             src0,         src1                      clamp
    v_add_u32_e64                   vdst,             src0,         src1                      clamp
    v_addc_co_u32_e64               vdst,       sdst, src0,         src1,        ssrc2        clamp
    v_alignbit_b32                  vdst,             src0,         src1,        src2:b16
    v_alignbyte_b32                 vdst,             src0,         src1,        src2:b16
    v_and_b32_e64                   vdst,             src0,         src1
    v_and_or_b32                    vdst,             src0,         src1,        src2
    v_ashrrev_i16_e64               vdst,             src0:u16,     src1
    v_ashrrev_i32_e64               vdst,             src0:u32,     src1
    v_ashrrev_i64                   vdst,             src0:u32,     src1
    v_bcnt_u32_b32                  vdst,             src0,         src1
    v_bfe_i32                       vdst,             src0,         src1:u32,    src2:u32
    v_bfe_u32                       vdst,             src0,         src1,        src2
    v_bfi_b32                       vdst,             src0,         src1,        src2
    v_bfm_b32                       vdst,             src0,         src1
    v_bfrev_b32_e64                 vdst,             src
    v_ceil_f16_e64                  vdst,             src:m                                   clamp omod
    v_ceil_f32_e64                  vdst,             src:m                                   clamp omod
    v_ceil_f64_e64                  vdst,             src:m                                   clamp omod
    v_clrexcp_e64
    v_cmp_class_f16_e64             sdst,             src0:m,       src1:b32
    v_cmp_class_f32_e64             sdst,             src0:m,       src1:b32
    v_cmp_class_f64_e64             sdst,             src0:m,       src1:b32
    v_cmp_eq_f16_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_eq_f32_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_eq_f64_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_eq_i16_e64                sdst,             src0,         src1
    v_cmp_eq_i32_e64                sdst,             src0,         src1
    v_cmp_eq_i64_e64                sdst,             src0,         src1
    v_cmp_eq_u16_e64                sdst,             src0,         src1
    v_cmp_eq_u32_e64                sdst,             src0,         src1
    v_cmp_eq_u64_e64                sdst,             src0,         src1
    v_cmp_f_f16_e64                 sdst,             src0:m,       src1:m                    clamp
    v_cmp_f_f32_e64                 sdst,             src0:m,       src1:m                    clamp
    v_cmp_f_f64_e64                 sdst,             src0:m,       src1:m                    clamp
    v_cmp_f_i16_e64                 sdst,             src0,         src1
    v_cmp_f_i32_e64                 sdst,             src0,         src1
    v_cmp_f_i64_e64                 sdst,             src0,         src1
    v_cmp_f_u16_e64                 sdst,             src0,         src1
    v_cmp_f_u32_e64                 sdst,             src0,         src1
    v_cmp_f_u64_e64                 sdst,             src0,         src1
    v_cmp_ge_f16_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_ge_f32_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_ge_f64_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_ge_i16_e64                sdst,             src0,         src1
    v_cmp_ge_i32_e64                sdst,             src0,         src1
    v_cmp_ge_i64_e64                sdst,             src0,         src1
    v_cmp_ge_u16_e64                sdst,             src0,         src1
    v_cmp_ge_u32_e64                sdst,             src0,         src1
    v_cmp_ge_u64_e64                sdst,             src0,         src1
    v_cmp_gt_f16_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_gt_f32_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_gt_f64_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_gt_i16_e64                sdst,             src0,         src1
    v_cmp_gt_i32_e64                sdst,             src0,         src1
    v_cmp_gt_i64_e64                sdst,             src0,         src1
    v_cmp_gt_u16_e64                sdst,             src0,         src1
    v_cmp_gt_u32_e64                sdst,             src0,         src1
    v_cmp_gt_u64_e64                sdst,             src0,         src1
    v_cmp_le_f16_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_le_f32_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_le_f64_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_le_i16_e64                sdst,             src0,         src1
    v_cmp_le_i32_e64                sdst,             src0,         src1
    v_cmp_le_i64_e64                sdst,             src0,         src1
    v_cmp_le_u16_e64                sdst,             src0,         src1
    v_cmp_le_u32_e64                sdst,             src0,         src1
    v_cmp_le_u64_e64                sdst,             src0,         src1
    v_cmp_lg_f16_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_lg_f32_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_lg_f64_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_lt_f16_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_lt_f32_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_lt_f64_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmp_lt_i16_e64                sdst,             src0,         src1
    v_cmp_lt_i32_e64                sdst,             src0,         src1
    v_cmp_lt_i64_e64                sdst,             src0,         src1
    v_cmp_lt_u16_e64                sdst,             src0,         src1
    v_cmp_lt_u32_e64                sdst,             src0,         src1
    v_cmp_lt_u64_e64                sdst,             src0,         src1
    v_cmp_ne_i16_e64                sdst,             src0,         src1
    v_cmp_ne_i32_e64                sdst,             src0,         src1
    v_cmp_ne_i64_e64                sdst,             src0,         src1
    v_cmp_ne_u16_e64                sdst,             src0,         src1
    v_cmp_ne_u32_e64                sdst,             src0,         src1
    v_cmp_ne_u64_e64                sdst,             src0,         src1
    v_cmp_neq_f16_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_neq_f32_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_neq_f64_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_nge_f16_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_nge_f32_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_nge_f64_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_ngt_f16_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_ngt_f32_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_ngt_f64_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_nle_f16_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_nle_f32_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_nle_f64_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_nlg_f16_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_nlg_f32_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_nlg_f64_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_nlt_f16_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_nlt_f32_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_nlt_f64_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_o_f16_e64                 sdst,             src0:m,       src1:m                    clamp
    v_cmp_o_f32_e64                 sdst,             src0:m,       src1:m                    clamp
    v_cmp_o_f64_e64                 sdst,             src0:m,       src1:m                    clamp
    v_cmp_t_i16_e64                 sdst,             src0,         src1
    v_cmp_t_i32_e64                 sdst,             src0,         src1
    v_cmp_t_i64_e64                 sdst,             src0,         src1
    v_cmp_t_u16_e64                 sdst,             src0,         src1
    v_cmp_t_u32_e64                 sdst,             src0,         src1
    v_cmp_t_u64_e64                 sdst,             src0,         src1
    v_cmp_tru_f16_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_tru_f32_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_tru_f64_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmp_u_f16_e64                 sdst,             src0:m,       src1:m                    clamp
    v_cmp_u_f32_e64                 sdst,             src0:m,       src1:m                    clamp
    v_cmp_u_f64_e64                 sdst,             src0:m,       src1:m                    clamp
    v_cmpx_class_f16_e64            sdst,             src0:m,       src1:b32
    v_cmpx_class_f32_e64            sdst,             src0:m,       src1:b32
    v_cmpx_class_f64_e64            sdst,             src0:m,       src1:b32
    v_cmpx_eq_f16_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_eq_f32_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_eq_f64_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_eq_i16_e64               sdst,             src0,         src1
    v_cmpx_eq_i32_e64               sdst,             src0,         src1
    v_cmpx_eq_i64_e64               sdst,             src0,         src1
    v_cmpx_eq_u16_e64               sdst,             src0,         src1
    v_cmpx_eq_u32_e64               sdst,             src0,         src1
    v_cmpx_eq_u64_e64               sdst,             src0,         src1
    v_cmpx_f_f16_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmpx_f_f32_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmpx_f_f64_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmpx_f_i16_e64                sdst,             src0,         src1
    v_cmpx_f_i32_e64                sdst,             src0,         src1
    v_cmpx_f_i64_e64                sdst,             src0,         src1
    v_cmpx_f_u16_e64                sdst,             src0,         src1
    v_cmpx_f_u32_e64                sdst,             src0,         src1
    v_cmpx_f_u64_e64                sdst,             src0,         src1
    v_cmpx_ge_f16_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_ge_f32_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_ge_f64_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_ge_i16_e64               sdst,             src0,         src1
    v_cmpx_ge_i32_e64               sdst,             src0,         src1
    v_cmpx_ge_i64_e64               sdst,             src0,         src1
    v_cmpx_ge_u16_e64               sdst,             src0,         src1
    v_cmpx_ge_u32_e64               sdst,             src0,         src1
    v_cmpx_ge_u64_e64               sdst,             src0,         src1
    v_cmpx_gt_f16_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_gt_f32_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_gt_f64_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_gt_i16_e64               sdst,             src0,         src1
    v_cmpx_gt_i32_e64               sdst,             src0,         src1
    v_cmpx_gt_i64_e64               sdst,             src0,         src1
    v_cmpx_gt_u16_e64               sdst,             src0,         src1
    v_cmpx_gt_u32_e64               sdst,             src0,         src1
    v_cmpx_gt_u64_e64               sdst,             src0,         src1
    v_cmpx_le_f16_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_le_f32_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_le_f64_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_le_i16_e64               sdst,             src0,         src1
    v_cmpx_le_i32_e64               sdst,             src0,         src1
    v_cmpx_le_i64_e64               sdst,             src0,         src1
    v_cmpx_le_u16_e64               sdst,             src0,         src1
    v_cmpx_le_u32_e64               sdst,             src0,         src1
    v_cmpx_le_u64_e64               sdst,             src0,         src1
    v_cmpx_lg_f16_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_lg_f32_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_lg_f64_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_lt_f16_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_lt_f32_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_lt_f64_e64               sdst,             src0:m,       src1:m                    clamp
    v_cmpx_lt_i16_e64               sdst,             src0,         src1
    v_cmpx_lt_i32_e64               sdst,             src0,         src1
    v_cmpx_lt_i64_e64               sdst,             src0,         src1
    v_cmpx_lt_u16_e64               sdst,             src0,         src1
    v_cmpx_lt_u32_e64               sdst,             src0,         src1
    v_cmpx_lt_u64_e64               sdst,             src0,         src1
    v_cmpx_ne_i16_e64               sdst,             src0,         src1
    v_cmpx_ne_i32_e64               sdst,             src0,         src1
    v_cmpx_ne_i64_e64               sdst,             src0,         src1
    v_cmpx_ne_u16_e64               sdst,             src0,         src1
    v_cmpx_ne_u32_e64               sdst,             src0,         src1
    v_cmpx_ne_u64_e64               sdst,             src0,         src1
    v_cmpx_neq_f16_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_neq_f32_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_neq_f64_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_nge_f16_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_nge_f32_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_nge_f64_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_ngt_f16_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_ngt_f32_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_ngt_f64_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_nle_f16_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_nle_f32_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_nle_f64_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_nlg_f16_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_nlg_f32_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_nlg_f64_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_nlt_f16_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_nlt_f32_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_nlt_f64_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_o_f16_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmpx_o_f32_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmpx_o_f64_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmpx_t_i16_e64                sdst,             src0,         src1
    v_cmpx_t_i32_e64                sdst,             src0,         src1
    v_cmpx_t_i64_e64                sdst,             src0,         src1
    v_cmpx_t_u16_e64                sdst,             src0,         src1
    v_cmpx_t_u32_e64                sdst,             src0,         src1
    v_cmpx_t_u64_e64                sdst,             src0,         src1
    v_cmpx_tru_f16_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_tru_f32_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_tru_f64_e64              sdst,             src0:m,       src1:m                    clamp
    v_cmpx_u_f16_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmpx_u_f32_e64                sdst,             src0:m,       src1:m                    clamp
    v_cmpx_u_f64_e64                sdst,             src0:m,       src1:m                    clamp
    v_cndmask_b32_e64               vdst,             src0:m,       src1:m,      ssrc2
    v_cos_f16_e64                   vdst,             src:m                                   clamp omod
    v_cos_f32_e64                   vdst,             src:m                                   clamp omod
    v_cubeid_f32                    vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_cubema_f32                    vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_cubesc_f32                    vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_cubetc_f32                    vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_cvt_f16_f32_e64               vdst,             src:m                                   clamp omod
    v_cvt_f16_i16_e64               vdst,             src                                     clamp omod
    v_cvt_f16_u16_e64               vdst,             src                                     clamp omod
    v_cvt_f32_f16_e64               vdst,             src:m                                   clamp omod
    v_cvt_f32_f64_e64               vdst,             src:m                                   clamp omod
    v_cvt_f32_i32_e64               vdst,             src                                     clamp omod
    v_cvt_f32_u32_e64               vdst,             src                                     clamp omod
    v_cvt_f32_ubyte0_e64            vdst,             src                                     clamp omod
    v_cvt_f32_ubyte1_e64            vdst,             src                                     clamp omod
    v_cvt_f32_ubyte2_e64            vdst,             src                                     clamp omod
    v_cvt_f32_ubyte3_e64            vdst,             src                                     clamp omod
    v_cvt_f64_f32_e64               vdst,             src:m                                   clamp omod
    v_cvt_f64_i32_e64               vdst,             src                                     clamp omod
    v_cvt_f64_u32_e64               vdst,             src                                     clamp omod
    v_cvt_flr_i32_f32_e64           vdst,             src:m
    v_cvt_i16_f16_e64               vdst,             src:m                                   clamp
    v_cvt_i32_f32_e64               vdst,             src:m                                   clamp
    v_cvt_i32_f64_e64               vdst,             src:m                                   clamp
    v_cvt_norm_i16_f16_e64          vdst,             src:m                                   clamp
    v_cvt_norm_u16_f16_e64          vdst,             src:m                                   clamp
    v_cvt_off_f32_i4_e64            vdst,             src                                     clamp omod
    v_cvt_pk_i16_i32                vdst,             src0:i32,     src1:i32
    v_cvt_pk_u16_u32                vdst,             src0:u32,     src1:u32
    v_cvt_pk_u8_f32                 vdst:b32,         src0:m:f32,   src1:u32,    src2:u32
    v_cvt_pkaccum_u8_f32            vdst:b32,         src0:m:f32,   src1:u32
    v_cvt_pknorm_i16_f16            vdst,             src0:m:f16,   src1:m:f16                op_sel
    v_cvt_pknorm_i16_f32            vdst,             src0:m:f32,   src1:m:f32
    v_cvt_pknorm_u16_f16            vdst,             src0:m:f16,   src1:m:f16                op_sel
    v_cvt_pknorm_u16_f32            vdst,             src0:m:f32,   src1:m:f32
    v_cvt_pkrtz_f16_f32             vdst,             src0:m:f32,   src1:m:f32
    v_cvt_rpi_i32_f32_e64           vdst,             src:m
    v_cvt_u16_f16_e64               vdst,             src:m                                   clamp
    v_cvt_u32_f32_e64               vdst,             src:m                                   clamp
    v_cvt_u32_f64_e64               vdst,             src:m                                   clamp
    v_div_fixup_f16                 vdst,             src0:m,       src1:m,      src2:m       op_sel clamp omod
    v_div_fixup_f32                 vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_div_fixup_f64                 vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_div_fixup_legacy_f16          vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_div_fmas_f32                  vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_div_fmas_f64                  vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_div_scale_f32                 vdst,       vcc,  src0,         src1,        src2
    v_div_scale_f64                 vdst,       vcc,  src0,         src1,        src2
    v_dot2c_f32_f16_e64             vdst,             src0:m:f16x2, src1:m:f16x2              clamp omod
    v_dot2c_i32_i16_e64             vdst,             src0:i16x2,   src1:i16x2                clamp
    v_dot4c_i32_i8_e64              vdst,             src0:i8x4,    src1:i8x4                 clamp
    v_dot8c_i32_i4_e64              vdst,             src0:i4x8,    src1:i4x8                 clamp
    v_exp_f16_e64                   vdst,             src:m                                   clamp omod
    v_exp_f32_e64                   vdst,             src:m                                   clamp omod
    v_exp_legacy_f32_e64            vdst,             src:m                                   clamp omod
    v_ffbh_i32_e64                  vdst,             src
    v_ffbh_u32_e64                  vdst,             src
    v_ffbl_b32_e64                  vdst,             src
    v_floor_f16_e64                 vdst,             src:m                                   clamp omod
    v_floor_f32_e64                 vdst,             src:m                                   clamp omod
    v_floor_f64_e64                 vdst,             src:m                                   clamp omod
    v_fma_f16                       vdst,             src0:m,       src1:m,      src2:m       op_sel clamp omod
    v_fma_f32                       vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_fma_f64                       vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_fma_legacy_f16                vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_fmac_f32_e64                  vdst,             src0:m,       src1:m                    clamp omod
    v_fmac_f64_e64                  vdst,             src0:m,       src1:m                    clamp omod
    v_fract_f16_e64                 vdst,             src:m                                   clamp omod
    v_fract_f32_e64                 vdst,             src:m                                   clamp omod
    v_fract_f64_e64                 vdst,             src:m                                   clamp omod
    v_frexp_exp_i16_f16_e64         vdst,             src:m
    v_frexp_exp_i32_f32_e64         vdst,             src:m
    v_frexp_exp_i32_f64_e64         vdst,             src:m
    v_frexp_mant_f16_e64            vdst,             src:m                                   clamp omod
    v_frexp_mant_f32_e64            vdst,             src:m                                   clamp omod
    v_frexp_mant_f64_e64            vdst,             src:m                                   clamp omod
    v_ldexp_f16_e64                 vdst,             src0:m,       src1:i16                  clamp omod
    v_ldexp_f32                     vdst,             src0:m,       src1:i32                  clamp omod
    v_ldexp_f64                     vdst,             src0:m,       src1:i32                  clamp omod
    v_lerp_u8                       vdst:u32,         src0:b32,     src1:b32,    src2:b32
    v_log_f16_e64                   vdst,             src:m                                   clamp omod
    v_log_f32_e64                   vdst,             src:m                                   clamp omod
    v_log_legacy_f32_e64            vdst,             src:m                                   clamp omod
    v_lshl_add_u32                  vdst,             src0,         src1,        src2
    v_lshl_or_b32                   vdst,             src0,         src1:u32,    src2
    v_lshlrev_b16_e64               vdst,             src0:u16,     src1
    v_lshlrev_b32_e64               vdst,             src0:u32,     src1
    v_lshlrev_b64                   vdst,             src0:u32,     src1
    v_lshrrev_b16_e64               vdst,             src0:u16,     src1
    v_lshrrev_b32_e64               vdst,             src0:u32,     src1
    v_lshrrev_b64                   vdst,             src0:u32,     src1
    v_mac_f16_e64                   vdst,             src0:m,       src1:m                    clamp omod
    v_mac_f32_e64                   vdst,             src0:m,       src1:m                    clamp omod
    v_mad_f16                       vdst,             src0:m,       src1:m,      src2:m       op_sel clamp omod
    v_mad_f32                       vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_mad_i16                       vdst,             src0,         src1,        src2         op_sel clamp
    v_mad_i32_i16                   vdst,             src0,         src1,        src2:i32     op_sel clamp
    v_mad_i32_i24                   vdst,             src0,         src1,        src2:i32     clamp
    v_mad_i64_i32                   vdst,       sdst, src0,         src1,        src2:i64     clamp
    v_mad_legacy_f16                vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_mad_legacy_f32                vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_mad_legacy_i16                vdst,             src0,         src1,        src2         clamp
    v_mad_legacy_u16                vdst,             src0,         src1,        src2         clamp
    v_mad_u16                       vdst,             src0,         src1,        src2         op_sel clamp
    v_mad_u32_u16                   vdst,             src0,         src1,        src2:u32     op_sel clamp
    v_mad_u32_u24                   vdst,             src0,         src1,        src2:u32     clamp
    v_mad_u64_u32                   vdst,       sdst, src0,         src1,        src2:u64     clamp
    v_max3_f16                      vdst,             src0:m,       src1:m,      src2:m       op_sel clamp omod
    v_max3_f32                      vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_max3_i16                      vdst,             src0,         src1,        src2         op_sel
    v_max3_i32                      vdst,             src0,         src1,        src2
    v_max3_u16                      vdst,             src0,         src1,        src2         op_sel
    v_max3_u32                      vdst,             src0,         src1,        src2
    v_max_f16_e64                   vdst,             src0:m,       src1:m                    clamp omod
    v_max_f32_e64                   vdst,             src0:m,       src1:m                    clamp omod
    v_max_f64                       vdst,             src0:m,       src1:m                    clamp omod
    v_max_i16_e64                   vdst,             src0,         src1
    v_max_i32_e64                   vdst,             src0,         src1
    v_max_u16_e64                   vdst,             src0,         src1
    v_max_u32_e64                   vdst,             src0,         src1
    v_mbcnt_hi_u32_b32              vdst,             src0,         src1
    v_mbcnt_lo_u32_b32              vdst,             src0,         src1
    v_med3_f16                      vdst,             src0:m,       src1:m,      src2:m       op_sel clamp omod
    v_med3_f32                      vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_med3_i16                      vdst,             src0,         src1,        src2         op_sel
    v_med3_i32                      vdst,             src0,         src1,        src2
    v_med3_u16                      vdst,             src0,         src1,        src2         op_sel
    v_med3_u32                      vdst,             src0,         src1,        src2
    v_min3_f16                      vdst,             src0:m,       src1:m,      src2:m       op_sel clamp omod
    v_min3_f32                      vdst,             src0:m,       src1:m,      src2:m       clamp omod
    v_min3_i16                      vdst,             src0,         src1,        src2         op_sel
    v_min3_i32                      vdst,             src0,         src1,        src2
    v_min3_u16                      vdst,             src0,         src1,        src2         op_sel
    v_min3_u32                      vdst,             src0,         src1,        src2
    v_min_f16_e64                   vdst,             src0:m,       src1:m                    clamp omod
    v_min_f32_e64                   vdst,             src0:m,       src1:m                    clamp omod
    v_min_f64                       vdst,             src0:m,       src1:m                    clamp omod
    v_min_i16_e64                   vdst,             src0,         src1
    v_min_i32_e64                   vdst,             src0,         src1
    v_min_u16_e64                   vdst,             src0,         src1
    v_min_u32_e64                   vdst,             src0,         src1
    v_mov_b32_e64                   vdst,             src
    v_mqsad_pk_u16_u8               vdst:u16x4,       src0:u8x8,    src1:u8x4,   src2:u16x4   clamp
    v_mqsad_u32_u8                  vdst:u32x4,       src0:u8x8,    src1:u8x4,   vsrc2:u32x4  clamp
    v_msad_u8                       vdst:u32,         src0:u8x4,    src1:u8x4,   src2:u32     clamp
    v_mul_f16_e64                   vdst,             src0:m,       src1:m                    clamp omod
    v_mul_f32_e64                   vdst,             src0:m,       src1:m                    clamp omod
    v_mul_f64                       vdst,             src0:m,       src1:m                    clamp omod
    v_mul_hi_i32                    vdst,             src0,         src1
    v_mul_hi_i32_i24_e64            vdst,             src0,         src1
    v_mul_hi_u32                    vdst,             src0,         src1
    v_mul_hi_u32_u24_e64            vdst,             src0,         src1
    v_mul_i32_i24_e64               vdst,             src0,         src1                      clamp
    v_mul_legacy_f32                vdst,             src0:m,       src1:m                    clamp omod
    v_mul_lo_u16_e64                vdst,             src0,         src1
    v_mul_lo_u32                    vdst,             src0,         src1
    v_mul_u32_u24_e64               vdst,             src0,         src1                      clamp
    v_nop_e64
    v_not_b32_e64                   vdst,             src
    v_or3_b32                       vdst,             src0,         src1,        src2
    v_or_b32_e64                    vdst,             src0,         src1
    v_pack_b32_f16                  vdst,             src0:m,       src1:m                    op_sel
    v_perm_b32                      vdst,             src0,         src1,        src2
    v_qsad_pk_u16_u8                vdst:u16x4,       src0:u8x8,    src1:u8x4,   src2:u16x4   clamp
    v_rcp_f16_e64                   vdst,             src:m                                   clamp omod
    v_rcp_f32_e64                   vdst,             src:m                                   clamp omod
    v_rcp_f64_e64                   vdst,             src:m                                   clamp omod
    v_rcp_iflag_f32_e64             vdst,             src:m                                   clamp omod
    v_readlane_b32                  sdst,             vsrc0,        ssrc1
    v_rndne_f16_e64                 vdst,             src:m                                   clamp omod
    v_rndne_f32_e64                 vdst,             src:m                                   clamp omod
    v_rndne_f64_e64                 vdst,             src:m                                   clamp omod
    v_rsq_f16_e64                   vdst,             src:m                                   clamp omod
    v_rsq_f32_e64                   vdst,             src:m                                   clamp omod
    v_rsq_f64_e64                   vdst,             src:m                                   clamp omod
    v_sad_hi_u8                     vdst:u32,         src0:u8x4,    src1:u8x4,   src2:u32     clamp
    v_sad_u16                       vdst:u32,         src0:u16x2,   src1:u16x2,  src2:u32     clamp
    v_sad_u32                       vdst,             src0,         src1,        src2         clamp
    v_sad_u8                        vdst:u32,         src0:u8x4,    src1:u8x4,   src2:u32     clamp
    v_sat_pk_u8_i16_e64             vdst:u8x4,        src
    v_screen_partition_4se_b32_e64  vdst,             src
    v_sin_f16_e64                   vdst,             src:m                                   clamp omod
    v_sin_f32_e64                   vdst,             src:m                                   clamp omod
    v_sqrt_f16_e64                  vdst,             src:m                                   clamp omod
    v_sqrt_f32_e64                  vdst,             src:m                                   clamp omod
    v_sqrt_f64_e64                  vdst,             src:m                                   clamp omod
    v_sub_co_u32_e64                vdst,       sdst, src0,         src1                      clamp
    v_sub_f16_e64                   vdst,             src0:m,       src1:m                    clamp omod
    v_sub_f32_e64                   vdst,             src0:m,       src1:m                    clamp omod
    v_sub_i16                       vdst,             src0,         src1                      op_sel clamp
    v_sub_i32                       vdst,             src0,         src1                      clamp
    v_sub_u16_e64                   vdst,             src0,         src1                      clamp
    v_sub_u32_e64                   vdst,             src0,         src1                      clamp
    v_subb_co_u32_e64               vdst,       sdst, src0,         src1,        ssrc2        clamp
    v_subbrev_co_u32_e64            vdst,       sdst, src0,         src1,        ssrc2        clamp
    v_subrev_co_u32_e64             vdst,       sdst, src0,         src1                      clamp
    v_subrev_f16_e64                vdst,             src0:m,       src1:m                    clamp omod
    v_subrev_f32_e64                vdst,             src0:m,       src1:m                    clamp omod
    v_subrev_u16_e64                vdst,             src0,         src1                      clamp
    v_subrev_u32_e64                vdst,             src0,         src1                      clamp
    v_trig_preop_f64                vdst,             src0:m,       src1:u32                  clamp omod
    v_trunc_f16_e64                 vdst,             src:m                                   clamp omod
    v_trunc_f32_e64                 vdst,             src:m                                   clamp omod
    v_trunc_f64_e64                 vdst,             src:m                                   clamp omod
    v_writelane_b32                 vdst,             ssrc0,        ssrc1
    v_xad_u32                       vdst,             src0,         src1,        src2
    v_xnor_b32_e64                  vdst,             src0,         src1
    v_xor_b32_e64                   vdst,             src0,         src1

### VOP3P

    INSTRUCTION                 DST          SRC0          SRC1          SRC2         MODIFIERS
    ——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
    v_accvgpr_read_b32          vdst,        vsrc
    v_accvgpr_write_b32         vdst,        src
    v_dot2_f32_f16              vdst,        src0:f16x2,   src1:f16x2,   src2:f32     neg_lo neg_hi clamp
    v_dot2_i32_i16              vdst,        src0:i16x2,   src1:i16x2,   src2:i32     clamp
    v_dot2_u32_u16              vdst,        src0:u16x2,   src1:u16x2,   src2:u32     clamp
    v_dot4_i32_i8               vdst,        src0:i8x4,    src1:i8x4,    src2:i32     clamp
    v_dot4_u32_u8               vdst,        src0:u8x4,    src1:u8x4,    src2:u32     clamp
    v_dot8_i32_i4               vdst,        src0:i4x8,    src1:i4x8,    src2:i32     clamp
    v_dot8_u32_u4               vdst,        src0:u4x8,    src1:u4x8,    src2:u32     clamp
    v_fma_mix_f32               vdst,        src0:m:fx,    src1:m:fx,    src2:m:fx    m_op_sel m_op_sel_hi clamp
    v_fma_mixhi_f16             vdst,        src0:m:fx,    src1:m:fx,    src2:m:fx    m_op_sel m_op_sel_hi clamp
    v_fma_mixlo_f16             vdst,        src0:m:fx,    src1:m:fx,    src2:m:fx    m_op_sel m_op_sel_hi clamp
    v_mfma_f32_16x16x16bf16_1k  vdst:f32x4,  vsrc0:bf16x4, vsrc1:bf16x4, src2:f32x4   cbsz abid blgp
    v_mfma_f32_16x16x16f16      vdst:f32x4,  vsrc0:f16x4,  vsrc1:f16x4,  src2:f32x4   cbsz abid blgp
    v_mfma_f32_16x16x1f32       vdst:f32x16, vsrc0:f32,    vsrc1:f32,    src2:f32x16  cbsz abid blgp
    v_mfma_f32_16x16x2bf16      vdst:f32x16, vsrc0:bf16x2, vsrc1:bf16x2, src2:f32x16  cbsz abid blgp
    v_mfma_f32_16x16x4bf16_1k   vdst:f32x16, vsrc0:bf16x4, vsrc1:bf16x4, src2:f32x16  cbsz abid blgp
    v_mfma_f32_16x16x4f16       vdst:f32x16, vsrc0:f16x4,  vsrc1:f16x4,  src2:f32x16  cbsz abid blgp
    v_mfma_f32_16x16x4f32       vdst:f32x4,  vsrc0:f32,    vsrc1:f32,    src2:f32x4   cbsz abid blgp
    v_mfma_f32_16x16x8bf16      vdst:f32x4,  vsrc0:bf16x2, vsrc1:bf16x2, src2:f32x4   cbsz abid blgp
    v_mfma_f32_32x32x1f32       vdst:f32x32, vsrc0:f32,    vsrc1:f32,    src2:f32x32  cbsz abid blgp
    v_mfma_f32_32x32x2bf16      vdst:f32x32, vsrc0:bf16x2, vsrc1:bf16x2, src2:f32x32  cbsz abid blgp
    v_mfma_f32_32x32x2f32       vdst:f32x16, vsrc0:f32,    vsrc1:f32,    src2:f32x16  cbsz abid blgp
    v_mfma_f32_32x32x4bf16      vdst:f32x16, vsrc0:bf16x2, vsrc1:bf16x2, src2:f32x16  cbsz abid blgp
    v_mfma_f32_32x32x4bf16_1k   vdst:f32x32, vsrc0:bf16x4, vsrc1:bf16x4, src2:f32x32  cbsz abid blgp
    v_mfma_f32_32x32x4f16       vdst:f32x32, vsrc0:f16x4,  vsrc1:f16x4,  src2:f32x32  cbsz abid blgp
    v_mfma_f32_32x32x8bf16_1k   vdst:f32x16, vsrc0:bf16x4, vsrc1:bf16x4, src2:f32x16  cbsz abid blgp
    v_mfma_f32_32x32x8f16       vdst:f32x16, vsrc0:f16x4,  vsrc1:f16x4,  src2:f32x16  cbsz abid blgp
    v_mfma_f32_4x4x1f32         vdst:f32x4,  vsrc0:f32,    vsrc1:f32,    src2:f32x4   cbsz abid blgp
    v_mfma_f32_4x4x2bf16        vdst:f32x4,  vsrc0:bf16x2, vsrc1:bf16x2, src2:f32x4   cbsz abid blgp
    v_mfma_f32_4x4x4bf16_1k     vdst:f32x4,  vsrc0:bf16x4, vsrc1:bf16x4, src2:f32x4   cbsz abid blgp
    v_mfma_f32_4x4x4f16         vdst:f32x4,  vsrc0:f16x4,  vsrc1:f16x4,  src2:f32x4   cbsz abid blgp
    v_mfma_f64_16x16x4f64       vdst:f64x4,  vsrc0:f64,    vsrc1:f64,    src2:f64x4   cbsz abid blgp
    v_mfma_f64_4x4x4f64         vdst:f64,    vsrc0:f64,    vsrc1:f64,    src2:f64     cbsz abid blgp
    v_mfma_i32_16x16x16i8       vdst:i32x4,  vsrc0:i8x4,   vsrc1:i8x4,   src2:i32x4   cbsz abid blgp
    v_mfma_i32_16x16x4i8        vdst:i32x16, vsrc0:i8x4,   vsrc1:i8x4,   src2:i32x16  cbsz abid blgp
    v_mfma_i32_32x32x4i8        vdst:i32x32, vsrc0:i8x4,   vsrc1:i8x4,   src2:i32x32  cbsz abid blgp
    v_mfma_i32_32x32x8i8        vdst:i32x16, vsrc0:i8x4,   vsrc1:i8x4,   src2:i32x16  cbsz abid blgp
    v_mfma_i32_4x4x4i8          vdst:i32x4,  vsrc0:i8x4,   vsrc1:i8x4,   src2:i32x4   cbsz abid blgp
    v_pk_add_f16                vdst,        src0,         src1                       op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_add_f32                vdst,        src0,         src1                       op_sel op_sel_hi
    v_pk_add_i16                vdst,        src0,         src1                       op_sel op_sel_hi clamp
    v_pk_add_u16                vdst,        src0,         src1                       op_sel op_sel_hi clamp
    v_pk_ashrrev_i16            vdst,        src0:u16x2,   src1                       op_sel op_sel_hi
    v_pk_fma_f16                vdst,        src0,         src1,         src2         op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_fma_f32                vdst,        src0,         src1,         src2         op_sel op_sel_hi
    v_pk_lshlrev_b16            vdst,        src0:u16x2,   src1                       op_sel op_sel_hi
    v_pk_lshrrev_b16            vdst,        src0:u16x2,   src1                       op_sel op_sel_hi
    v_pk_mad_i16                vdst,        src0,         src1,         src2         op_sel op_sel_hi clamp
    v_pk_mad_u16                vdst,        src0,         src1,         src2         op_sel op_sel_hi clamp
    v_pk_max_f16                vdst,        src0,         src1                       op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_max_i16                vdst,        src0,         src1                       op_sel op_sel_hi
    v_pk_max_u16                vdst,        src0,         src1                       op_sel op_sel_hi
    v_pk_min_f16                vdst,        src0,         src1                       op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_min_i16                vdst,        src0,         src1                       op_sel op_sel_hi
    v_pk_min_u16                vdst,        src0,         src1                       op_sel op_sel_hi
    v_pk_mov_b32                vdst,        src0,         src1                       op_sel op_sel_hi
    v_pk_mul_f16                vdst,        src0,         src1                       op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_mul_f32                vdst,        src0,         src1                       op_sel op_sel_hi
    v_pk_mul_lo_u16             vdst,        src0,         src1                       op_sel op_sel_hi
    v_pk_sub_i16                vdst,        src0,         src1                       op_sel op_sel_hi clamp
    v_pk_sub_u16                vdst,        src0,         src1                       op_sel op_sel_hi clamp

### VOPC

    INSTRUCTION                    DST       SRC0      SRC1            MODIFIERS
    ————————————————————————————————————————————————————————————————————————————————————
    v_cmp_class_f16                vcc,      src0,     vsrc1:b32
    v_cmp_class_f16_sdwa           sdst,     src0:m,   src1:m:b32      src0_sel src1_sel
    v_cmp_class_f32                vcc,      src0,     vsrc1:b32
    v_cmp_class_f32_sdwa           sdst,     src0:m,   src1:m:b32      src0_sel src1_sel
    v_cmp_class_f64                vcc,      src0,     vsrc1:b32
    v_cmp_eq_f16                   vcc,      src0,     vsrc1
    v_cmp_eq_f16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_eq_f32                   vcc,      src0,     vsrc1
    v_cmp_eq_f32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_eq_f64                   vcc,      src0,     vsrc1
    v_cmp_eq_i16                   vcc,      src0,     vsrc1
    v_cmp_eq_i16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_eq_i32                   vcc,      src0,     vsrc1
    v_cmp_eq_i32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_eq_i64                   vcc,      src0,     vsrc1
    v_cmp_eq_u16                   vcc,      src0,     vsrc1
    v_cmp_eq_u16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_eq_u32                   vcc,      src0,     vsrc1
    v_cmp_eq_u32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_eq_u64                   vcc,      src0,     vsrc1
    v_cmp_f_f16                    vcc,      src0,     vsrc1
    v_cmp_f_f16_sdwa               sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_f_f32                    vcc,      src0,     vsrc1
    v_cmp_f_f32_sdwa               sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_f_f64                    vcc,      src0,     vsrc1
    v_cmp_f_i16                    vcc,      src0,     vsrc1
    v_cmp_f_i16_sdwa               sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_f_i32                    vcc,      src0,     vsrc1
    v_cmp_f_i32_sdwa               sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_f_i64                    vcc,      src0,     vsrc1
    v_cmp_f_u16                    vcc,      src0,     vsrc1
    v_cmp_f_u16_sdwa               sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_f_u32                    vcc,      src0,     vsrc1
    v_cmp_f_u32_sdwa               sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_f_u64                    vcc,      src0,     vsrc1
    v_cmp_ge_f16                   vcc,      src0,     vsrc1
    v_cmp_ge_f16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_ge_f32                   vcc,      src0,     vsrc1
    v_cmp_ge_f32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_ge_f64                   vcc,      src0,     vsrc1
    v_cmp_ge_i16                   vcc,      src0,     vsrc1
    v_cmp_ge_i16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_ge_i32                   vcc,      src0,     vsrc1
    v_cmp_ge_i32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_ge_i64                   vcc,      src0,     vsrc1
    v_cmp_ge_u16                   vcc,      src0,     vsrc1
    v_cmp_ge_u16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_ge_u32                   vcc,      src0,     vsrc1
    v_cmp_ge_u32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_ge_u64                   vcc,      src0,     vsrc1
    v_cmp_gt_f16                   vcc,      src0,     vsrc1
    v_cmp_gt_f16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_gt_f32                   vcc,      src0,     vsrc1
    v_cmp_gt_f32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_gt_f64                   vcc,      src0,     vsrc1
    v_cmp_gt_i16                   vcc,      src0,     vsrc1
    v_cmp_gt_i16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_gt_i32                   vcc,      src0,     vsrc1
    v_cmp_gt_i32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_gt_i64                   vcc,      src0,     vsrc1
    v_cmp_gt_u16                   vcc,      src0,     vsrc1
    v_cmp_gt_u16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_gt_u32                   vcc,      src0,     vsrc1
    v_cmp_gt_u32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_gt_u64                   vcc,      src0,     vsrc1
    v_cmp_le_f16                   vcc,      src0,     vsrc1
    v_cmp_le_f16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_le_f32                   vcc,      src0,     vsrc1
    v_cmp_le_f32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_le_f64                   vcc,      src0,     vsrc1
    v_cmp_le_i16                   vcc,      src0,     vsrc1
    v_cmp_le_i16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_le_i32                   vcc,      src0,     vsrc1
    v_cmp_le_i32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_le_i64                   vcc,      src0,     vsrc1
    v_cmp_le_u16                   vcc,      src0,     vsrc1
    v_cmp_le_u16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_le_u32                   vcc,      src0,     vsrc1
    v_cmp_le_u32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_le_u64                   vcc,      src0,     vsrc1
    v_cmp_lg_f16                   vcc,      src0,     vsrc1
    v_cmp_lg_f16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_lg_f32                   vcc,      src0,     vsrc1
    v_cmp_lg_f32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_lg_f64                   vcc,      src0,     vsrc1
    v_cmp_lt_f16                   vcc,      src0,     vsrc1
    v_cmp_lt_f16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_lt_f32                   vcc,      src0,     vsrc1
    v_cmp_lt_f32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_lt_f64                   vcc,      src0,     vsrc1
    v_cmp_lt_i16                   vcc,      src0,     vsrc1
    v_cmp_lt_i16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_lt_i32                   vcc,      src0,     vsrc1
    v_cmp_lt_i32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_lt_i64                   vcc,      src0,     vsrc1
    v_cmp_lt_u16                   vcc,      src0,     vsrc1
    v_cmp_lt_u16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_lt_u32                   vcc,      src0,     vsrc1
    v_cmp_lt_u32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_lt_u64                   vcc,      src0,     vsrc1
    v_cmp_ne_i16                   vcc,      src0,     vsrc1
    v_cmp_ne_i16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_ne_i32                   vcc,      src0,     vsrc1
    v_cmp_ne_i32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_ne_i64                   vcc,      src0,     vsrc1
    v_cmp_ne_u16                   vcc,      src0,     vsrc1
    v_cmp_ne_u16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_ne_u32                   vcc,      src0,     vsrc1
    v_cmp_ne_u32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_ne_u64                   vcc,      src0,     vsrc1
    v_cmp_neq_f16                  vcc,      src0,     vsrc1
    v_cmp_neq_f16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_neq_f32                  vcc,      src0,     vsrc1
    v_cmp_neq_f32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_neq_f64                  vcc,      src0,     vsrc1
    v_cmp_nge_f16                  vcc,      src0,     vsrc1
    v_cmp_nge_f16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_nge_f32                  vcc,      src0,     vsrc1
    v_cmp_nge_f32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_nge_f64                  vcc,      src0,     vsrc1
    v_cmp_ngt_f16                  vcc,      src0,     vsrc1
    v_cmp_ngt_f16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_ngt_f32                  vcc,      src0,     vsrc1
    v_cmp_ngt_f32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_ngt_f64                  vcc,      src0,     vsrc1
    v_cmp_nle_f16                  vcc,      src0,     vsrc1
    v_cmp_nle_f16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_nle_f32                  vcc,      src0,     vsrc1
    v_cmp_nle_f32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_nle_f64                  vcc,      src0,     vsrc1
    v_cmp_nlg_f16                  vcc,      src0,     vsrc1
    v_cmp_nlg_f16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_nlg_f32                  vcc,      src0,     vsrc1
    v_cmp_nlg_f32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_nlg_f64                  vcc,      src0,     vsrc1
    v_cmp_nlt_f16                  vcc,      src0,     vsrc1
    v_cmp_nlt_f16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_nlt_f32                  vcc,      src0,     vsrc1
    v_cmp_nlt_f32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_nlt_f64                  vcc,      src0,     vsrc1
    v_cmp_o_f16                    vcc,      src0,     vsrc1
    v_cmp_o_f16_sdwa               sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_o_f32                    vcc,      src0,     vsrc1
    v_cmp_o_f32_sdwa               sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_o_f64                    vcc,      src0,     vsrc1
    v_cmp_t_i16                    vcc,      src0,     vsrc1
    v_cmp_t_i16_sdwa               sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_t_i32                    vcc,      src0,     vsrc1
    v_cmp_t_i32_sdwa               sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_t_i64                    vcc,      src0,     vsrc1
    v_cmp_t_u16                    vcc,      src0,     vsrc1
    v_cmp_t_u16_sdwa               sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_t_u32                    vcc,      src0,     vsrc1
    v_cmp_t_u32_sdwa               sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_t_u64                    vcc,      src0,     vsrc1
    v_cmp_tru_f16                  vcc,      src0,     vsrc1
    v_cmp_tru_f16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_tru_f32                  vcc,      src0,     vsrc1
    v_cmp_tru_f32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_tru_f64                  vcc,      src0,     vsrc1
    v_cmp_u_f16                    vcc,      src0,     vsrc1
    v_cmp_u_f16_sdwa               sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_u_f32                    vcc,      src0,     vsrc1
    v_cmp_u_f32_sdwa               sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmp_u_f64                    vcc,      src0,     vsrc1
    v_cmpx_class_f16               vcc,      src0,     vsrc1:b32
    v_cmpx_class_f16_sdwa          sdst,     src0:m,   src1:m:b32      src0_sel src1_sel
    v_cmpx_class_f32               vcc,      src0,     vsrc1:b32
    v_cmpx_class_f32_sdwa          sdst,     src0:m,   src1:m:b32      src0_sel src1_sel
    v_cmpx_class_f64               vcc,      src0,     vsrc1:b32
    v_cmpx_eq_f16                  vcc,      src0,     vsrc1
    v_cmpx_eq_f16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_eq_f32                  vcc,      src0,     vsrc1
    v_cmpx_eq_f32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_eq_f64                  vcc,      src0,     vsrc1
    v_cmpx_eq_i16                  vcc,      src0,     vsrc1
    v_cmpx_eq_i16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_eq_i32                  vcc,      src0,     vsrc1
    v_cmpx_eq_i32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_eq_i64                  vcc,      src0,     vsrc1
    v_cmpx_eq_u16                  vcc,      src0,     vsrc1
    v_cmpx_eq_u16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_eq_u32                  vcc,      src0,     vsrc1
    v_cmpx_eq_u32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_eq_u64                  vcc,      src0,     vsrc1
    v_cmpx_f_f16                   vcc,      src0,     vsrc1
    v_cmpx_f_f16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_f_f32                   vcc,      src0,     vsrc1
    v_cmpx_f_f32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_f_f64                   vcc,      src0,     vsrc1
    v_cmpx_f_i16                   vcc,      src0,     vsrc1
    v_cmpx_f_i16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_f_i32                   vcc,      src0,     vsrc1
    v_cmpx_f_i32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_f_i64                   vcc,      src0,     vsrc1
    v_cmpx_f_u16                   vcc,      src0,     vsrc1
    v_cmpx_f_u16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_f_u32                   vcc,      src0,     vsrc1
    v_cmpx_f_u32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_f_u64                   vcc,      src0,     vsrc1
    v_cmpx_ge_f16                  vcc,      src0,     vsrc1
    v_cmpx_ge_f16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_ge_f32                  vcc,      src0,     vsrc1
    v_cmpx_ge_f32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_ge_f64                  vcc,      src0,     vsrc1
    v_cmpx_ge_i16                  vcc,      src0,     vsrc1
    v_cmpx_ge_i16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_ge_i32                  vcc,      src0,     vsrc1
    v_cmpx_ge_i32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_ge_i64                  vcc,      src0,     vsrc1
    v_cmpx_ge_u16                  vcc,      src0,     vsrc1
    v_cmpx_ge_u16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_ge_u32                  vcc,      src0,     vsrc1
    v_cmpx_ge_u32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_ge_u64                  vcc,      src0,     vsrc1
    v_cmpx_gt_f16                  vcc,      src0,     vsrc1
    v_cmpx_gt_f16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_gt_f32                  vcc,      src0,     vsrc1
    v_cmpx_gt_f32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_gt_f64                  vcc,      src0,     vsrc1
    v_cmpx_gt_i16                  vcc,      src0,     vsrc1
    v_cmpx_gt_i16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_gt_i32                  vcc,      src0,     vsrc1
    v_cmpx_gt_i32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_gt_i64                  vcc,      src0,     vsrc1
    v_cmpx_gt_u16                  vcc,      src0,     vsrc1
    v_cmpx_gt_u16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_gt_u32                  vcc,      src0,     vsrc1
    v_cmpx_gt_u32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_gt_u64                  vcc,      src0,     vsrc1
    v_cmpx_le_f16                  vcc,      src0,     vsrc1
    v_cmpx_le_f16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_le_f32                  vcc,      src0,     vsrc1
    v_cmpx_le_f32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_le_f64                  vcc,      src0,     vsrc1
    v_cmpx_le_i16                  vcc,      src0,     vsrc1
    v_cmpx_le_i16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_le_i32                  vcc,      src0,     vsrc1
    v_cmpx_le_i32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_le_i64                  vcc,      src0,     vsrc1
    v_cmpx_le_u16                  vcc,      src0,     vsrc1
    v_cmpx_le_u16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_le_u32                  vcc,      src0,     vsrc1
    v_cmpx_le_u32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_le_u64                  vcc,      src0,     vsrc1
    v_cmpx_lg_f16                  vcc,      src0,     vsrc1
    v_cmpx_lg_f16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_lg_f32                  vcc,      src0,     vsrc1
    v_cmpx_lg_f32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_lg_f64                  vcc,      src0,     vsrc1
    v_cmpx_lt_f16                  vcc,      src0,     vsrc1
    v_cmpx_lt_f16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_lt_f32                  vcc,      src0,     vsrc1
    v_cmpx_lt_f32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_lt_f64                  vcc,      src0,     vsrc1
    v_cmpx_lt_i16                  vcc,      src0,     vsrc1
    v_cmpx_lt_i16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_lt_i32                  vcc,      src0,     vsrc1
    v_cmpx_lt_i32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_lt_i64                  vcc,      src0,     vsrc1
    v_cmpx_lt_u16                  vcc,      src0,     vsrc1
    v_cmpx_lt_u16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_lt_u32                  vcc,      src0,     vsrc1
    v_cmpx_lt_u32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_lt_u64                  vcc,      src0,     vsrc1
    v_cmpx_ne_i16                  vcc,      src0,     vsrc1
    v_cmpx_ne_i16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_ne_i32                  vcc,      src0,     vsrc1
    v_cmpx_ne_i32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_ne_i64                  vcc,      src0,     vsrc1
    v_cmpx_ne_u16                  vcc,      src0,     vsrc1
    v_cmpx_ne_u16_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_ne_u32                  vcc,      src0,     vsrc1
    v_cmpx_ne_u32_sdwa             sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_ne_u64                  vcc,      src0,     vsrc1
    v_cmpx_neq_f16                 vcc,      src0,     vsrc1
    v_cmpx_neq_f16_sdwa            sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_neq_f32                 vcc,      src0,     vsrc1
    v_cmpx_neq_f32_sdwa            sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_neq_f64                 vcc,      src0,     vsrc1
    v_cmpx_nge_f16                 vcc,      src0,     vsrc1
    v_cmpx_nge_f16_sdwa            sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_nge_f32                 vcc,      src0,     vsrc1
    v_cmpx_nge_f32_sdwa            sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_nge_f64                 vcc,      src0,     vsrc1
    v_cmpx_ngt_f16                 vcc,      src0,     vsrc1
    v_cmpx_ngt_f16_sdwa            sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_ngt_f32                 vcc,      src0,     vsrc1
    v_cmpx_ngt_f32_sdwa            sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_ngt_f64                 vcc,      src0,     vsrc1
    v_cmpx_nle_f16                 vcc,      src0,     vsrc1
    v_cmpx_nle_f16_sdwa            sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_nle_f32                 vcc,      src0,     vsrc1
    v_cmpx_nle_f32_sdwa            sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_nle_f64                 vcc,      src0,     vsrc1
    v_cmpx_nlg_f16                 vcc,      src0,     vsrc1
    v_cmpx_nlg_f16_sdwa            sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_nlg_f32                 vcc,      src0,     vsrc1
    v_cmpx_nlg_f32_sdwa            sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_nlg_f64                 vcc,      src0,     vsrc1
    v_cmpx_nlt_f16                 vcc,      src0,     vsrc1
    v_cmpx_nlt_f16_sdwa            sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_nlt_f32                 vcc,      src0,     vsrc1
    v_cmpx_nlt_f32_sdwa            sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_nlt_f64                 vcc,      src0,     vsrc1
    v_cmpx_o_f16                   vcc,      src0,     vsrc1
    v_cmpx_o_f16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_o_f32                   vcc,      src0,     vsrc1
    v_cmpx_o_f32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_o_f64                   vcc,      src0,     vsrc1
    v_cmpx_t_i16                   vcc,      src0,     vsrc1
    v_cmpx_t_i16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_t_i32                   vcc,      src0,     vsrc1
    v_cmpx_t_i32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_t_i64                   vcc,      src0,     vsrc1
    v_cmpx_t_u16                   vcc,      src0,     vsrc1
    v_cmpx_t_u16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_t_u32                   vcc,      src0,     vsrc1
    v_cmpx_t_u32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_t_u64                   vcc,      src0,     vsrc1
    v_cmpx_tru_f16                 vcc,      src0,     vsrc1
    v_cmpx_tru_f16_sdwa            sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_tru_f32                 vcc,      src0,     vsrc1
    v_cmpx_tru_f32_sdwa            sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_tru_f64                 vcc,      src0,     vsrc1
    v_cmpx_u_f16                   vcc,      src0,     vsrc1
    v_cmpx_u_f16_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_u_f32                   vcc,      src0,     vsrc1
    v_cmpx_u_f32_sdwa              sdst,     src0:m,   src1:m          src0_sel src1_sel
    v_cmpx_u_f64                   vcc,      src0,     vsrc1