MESSAGE
| DATE | 2015-01-28 |
| FROM | Ruben Safir
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| SUBJECT | Subject: [LIU Comp Sci] Operating Systems gibberish
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From owner-learn-outgoing-at-mrbrklyn.com Wed Jan 28 23:49:00 2015
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Date: Wed, 28 Jan 2015 23:48:58 -0500
From: Ruben Safir
To: learn-at-nylxs.com
Subject: [LIU Comp Sci] Operating Systems gibberish
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Anyone read chapter one and can explain this little part
Interrupts are an important part of a computer architecture. Each
computer design has its own interrupt mechanism, but several
functions are common. The interrupt must transfer control to the
appropriate interrupt service routine. The straightforward method
for handling this transfer would be to invoke a generic routine to
examine the interrupt information. The routine, in turn, would call
the interrupt-specific handler. However, interrupts must be handled
quickly. Since only a predefined number of interrupts is possible,
a table of pointers to interrupt routines can be used instead to
provide the necessary speed. The interrupt routine is called
indirectly through the table, with no intermediate routine needed.
Generally, the table of pointers is stored in low memory (the first
hundred or so locations). These locations hold the addresses of
the interrupt service routines for the various devices. This array,
or interrupt vector, of addresses is then indexed by a unique device
number, given with the interrupt request, to provide the address
of the interrupt service routine for the interrupting device.
Operating systems as different as Windows and UNIX dispatch interrupts
in this manner. The interrupt architecture must also save the
address of the interrupted instruction. Many old designs simply
stored the interrupt address in a fixed location or in a location
indexed by the device number. More recent architectures store the
return address on the system stack. If the interrupt routine needs
to modify the processor state?for instance, by modifying register
values?it must explicitly save the current state and then restore
that state before returning. After the interrupt is serviced, the
saved return address is loaded into the program counter, and the
interrupted computation resumes as though the interrupt had not
occurred.
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