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DATE 2014-12-01

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MESSAGE
DATE 2014-12-09
FROM Ruben Safir
SUBJECT Subject: [LIU Comp Sci] Machine Instructions notes
From owner-learn-outgoing-at-mrbrklyn.com Tue Dec 9 03:43:02 2014
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Date: Tue, 9 Dec 2014 03:43:00 -0500
From: Ruben Safir
To: learn-at-nylxs.com
Cc: Samir Iabbassen
Subject: [LIU Comp Sci] Machine Instructions notes
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This is up to assembler

I lose this guy half way through the slides and text. All of a sudden,
he is throwing this term around, Implicit, and never defining it.

I'm not thrilled with this text. He has sent me on the white rabbit
hunt before, trying to fill in the gaps of what is is saying. He is not
organized in his notes and paragraph structure. He just rambles, and so
do the notes then.

He goes through this whole specification on the x86 and the ARM and you
can spend a year on that...and tomorrow it will all be changed, if not
already changed. I wish he would stick to priniciples. You can always
apply the princiiples.


http://www.nylxs.com/docs/grad_school/arch/machine_instructions.txt.html


Machine Instructions and Optcodes

12.0 Elements of Machine Instructions

12.01 Operation Code:
.011 Specifies the operation to be performed

12.02 Source Operand Reference:
.021 Operation Inputs

12.03 Result Operand Reference:
.031 Where the result is stored if need be

12.04 Next Instruction Reference:
.032 Where the next instruction to execute is located
.033 The address can be real or virtual

12.1 Operand Sources:
12.11 Virtual or Main Memory
12.12 Processor Register
12.13 Immediate: The orperand is contained within a field of
the instruction being executed.
12.14 I/O device
12.15 Possible Instruction Layout
___________________________________________________________
| Opcode | Operand Reference | Operant Reference|
|___________________|____________________|__________________|
4 bits 6 bits 6 bit
Total 16 bits

12.151 IR - Instruction Register is where the instruction is read to
on the Control Unit.
12.152 Symbolic Representation:
1521 ADD
1522 SUB
1523 MUL
1524 DIV
1525 LOAD Load Data from memory
1526 STOR Store Data to memory

1527 Operands can also be referred to symbolically
ADD R Y

12.2 Instruction capabilities and Types:
The instruction set must be sufficient to able to perform any operation
that the computer hardware is capable of, either singularly or in
combination with each other.

12.21 Data Processing: Arithmetic and Logical Operations
12.22 Data Storage: Move Data into and out of memory and registers
12.23 I/O instruction: Remember those feisty I/O modules?
12.24 Control - Test and Branch

12.3 Address References: Usually one might need to reference 4 addresses
in an instuction cycle: Two Source Operands, a destination for output
Operand and the next instruction to execute.
12.31 Solutions to specific problems can be solved with one, two or three (or
more) operands
.311 Example:

Y = A-B
-----
C + (D*E)

.3112 Singular Operand - Assumes an Accumulator Register (AC)
LOAD D
MUL E
ADD C
STOR X
LOAD A
SUB B
DIV X
STOR Y

.3113 Double Operand:
Y = A MOV Y,A
Y <- Y - B SUB Y, B
D <- D * E MPY D, E
D <- D + C ADD D, C
Y <- Y / D Y DIV T

.3114 Triple Operand
T = A - B SUB T, A, B
L = D * C MTY L, D, E
L = L + C ADD L,L,C
Y = T/L DIV Y,T,L



12.32 There are trade offs among the differing techniques.
321 Multiple Addresses allow for use of fast registers for data storage
322 Few operands allow for more primitive processors and small
instruction size.
323 More addresses might leverage an expanded opcode set and differing
addressing schemes.
324 STACKS can use zero address instructions

12.33 Operand Set Design Issues:
QUOTE:
It may surprise you to know that some of the
most fundamental issues relating to the design
of instruction sets remain in dispute. Indeed,
in recent years, the level of disagreement
concerning these fundamentals has actually
grown. The most important of these fundamental
design issues include the following:

Operation repertoire: How many and which
operations to provide, and how complex operations
should be

Data types: The various types of data upon which
operations are performed

Instruction format: Instruction length (in bits),
number of addresses, size of various fields,
and so on

Registers: Number of processor registers that
can be referenced by instructions, and their use

Addressing: The mode or modes by which the
address of an operand is specified

These issues are highly interrelated and must be
considered together in designing an instruction
set. This book, of course, must consider them
in some sequence, but an attempt is made to show
the interrelationships.
UNQUOTE

12.4 Data Type: Numbers,
12.41 Numbers
12.412 Binary Integer or Binary Fixed Point
12.413 Binary Floating Point
12.414 Decimal
4141 Packed Decimal
41411 Each decimal digit is represented by a 4-bit code
41412 0000 => 1001 which is 0 -> 9
41413 4-bit codes are strung together, usually
in multiples of 8 bits from 0 -> 9999

41414 0000 0000 0000 0000 -> 1001 1001 1001 1001

41415 Standard sign values are 1100 for positive ( +)
and 1101 for negative ( -)

12.42 Characters
12.421 International Reference Alphabet (IRA) - ASCII
12.422 unique 7-bit pattern
12.423 128 different characters
12.424 some of the patterns represent control characters
12.425 transmitted using 8 bits per character
12.426 IRA bit pattern 011XXXX, the digits 0 through 9 are
represented by their binary equivalents, 0000 through 1001
12.4261 This is the same as the pack code

12.43 Logic Data: - Bitwise arrays which store arrays of True or False
information.



12.5 Architectural Example: x86

http://www.nylxs.com/images/x86_data_types.png

51 Byte, word (16 bits), doubleword (32 bits), quadword (64 bits), and
double quadword (128 bits) locations with arbitrary binary contents.

52 Integer: A signed binary value contained in a byte, word, or doubleword, using
twos complement representation.

53 Ordinal: An unsigned integer contained in a byte, word, or doubleword.

54 Unpacked binary coded decimal (BCD): A representation of a BCD digit in the range 0 through 9, with one
digit in each byte.

55 Near pointer: A 16-bit, 32-bit, or 64-bit effective address that represents the offset
within a segment. Used for all pointers in a nonsegmented memory and for references within a segment in a segmented memory.

56 Far pointer
A logical address consisting of a 16-bit segment selector and an offset
of 16, 32, or 64 bits. Far pointers are used for memory references in a
segmented memory model where the identity of a segment being
accessed must be specified explicitly.

57 Bit field
A contiguous sequence of bits in which the position of each bit is
considered as an independent unit. A bit string can begin at any bit
position of any byte and can contain up to 32 bits.

58 Bit string
A contiguous sequence of bits, containing from zero to 232 - 1 bits.

59 Byte string
A contiguous sequence of bytes, words, or doublewords, containing from
zero to 232 - 1 bytes.

5-10 Packed SIMD (single instruction, multiple data)
Packed 64-bit and 128-bit data types (MMX)


5-11 Floating Points:
http://www.nylxs.com/images/x86_float.png
Notice the 2's complements


12.6 Types of Operations:
.61 Data Transfer -
.62 Arithmetic
.63 Logical - ADD, OR, NOT, SHIFT, ROTATE etc
.64 Conversion - TRANSLATE, CONVERT
.65 I/O - INPUT, OUTPUT, TEST
.66 System Control - ??
.67 Transfer Control - Jump, Return, Execute


13.0 Address Modes:
.01 Immediate
.02 Direct
.03 Indirect
.04 Register
.05 Register Indirect
.06 Displacement
.07 Stack

13.1 The CPU has to determine with method it needs to use to interpret
instructions
13.11 Often, different opcodes will use different addressing modes.
13.12 One or more bits in the instruction format can be used as a
mode field.
13.13 Effective Address: ==> without virtual memory it is the address in
Memory of a Register

13.131 In a virtual memory system, the effective address is a
virtual address or a register.

13.132 The actual mapping to a physical address is a function
of the memory management unit (MMU) and is invisible to the
programmer.

13.2 Immediate Address Mode: Operand = A;
13.21 Most immediate form
13.22 Used to define constants, set initial values of variables
13.23 Typically numbers are assigned in Two's Compliment Form
13.24 When loaded into a data register, the signed bit is moved to the
extreme left of the word size.
13.25 In some cases, the immediate binary value is interpreted as an
unsigned nonnegative integer.
13.26 No memory reference other than the instruction fetch is required
to obtain the operand
13.27 The size of the number is restricted to the size of the address
field, which, in most instruction sets, is small compared with the
word length.

13.3 Direct Addressing: EA = A
13.31 The address field contains the effect address of the operand
13.32 Only one memory reference and no special calculation

[ ]
----------------------------- [ ]
|[optcode]|[ A ]|==> [ Operand ] (location address stored in
----------------------------- [ ] A in the instruction )
[ ]
[ ]
[ ]
[ ]

Memory


13.4 Indirect Addressing: EA = (A)
13.41 Address field refers to the address of a word in memory, which in turn contains a full-length
address of the operand.
.411 This is a different mode than we have seen thus far. The total
addressing of the CPU is limited by the width of A. From there,
the total addressable memory locations can be extended by the
size of (2^ Word) by reading addresses from full memory locations

.412 Parenthesis means Contents Of => (A) is Contents within A

.412 If k is the number of bites of the Address Space A in the
instruction code, then although this method allows for access
of 2^N (where N is a Word Size), only 2^K addresses can be
accessed at any time (a subset of 2^N).

.413 In a virtual memory environment, all the effective address
locations can be confined to page 0 of any process, which can be
described within the limits of 2^K.
.414 When a process is active, there will be repeated references to
page 0, (inside a set of 2^K addreses) It therefor remains in real memory.
.4141 Thus, an indirect memory reference will involve, at most, one page
fault rather than two.

13.5 Register Addressing: EA = R

13.51 Similar to Direct Addressing
13.52 The operand is sitting in the register
13.53 Typically, an address field that references registers will have from 3 to 5 bits,
so that a total of from 8 to 32 general-purpose registers can be referenced.
13.54 In particular, suppose that the algorithm for twos complement multiplication were to
be implemented in software.

13.6 Register Indirect Addressing: EA = (R)
13.61 Same an indirect addressing but instead of reading a memory location
for an memory address that contains the operand, here well pull up a
register. The address in the register is a memory location for an
operand.

13.7 Displacement Addressing: EA = A + (R)
13.71 The Instruction has Two A fields
13.711 One of the A fields is explicit
13.712 The other is an implicit reference according to the optcode.
.7121 refers to a register whose contents are added to A to produce
the effective address.

13.713 Examples:
7131 Relative Addressing or PC-Relative Addressing
311 Implicitly referenced register is a program counter
312 added to the Address field of the Instruct to form an EA
313 Address field is normally a two complement number for this
purpose
314 Thus, the effective address is a displacement relative to the
address of the instruction.

7132 Base register Addressing: The register contains a main memory
address and the A field is an offset.
321 Implements Segmentation

7133 Indexing - the opposite of register addressing where the
offset is in the register and A is the main memory location.
331 Efficient mechanism for performing iterative operations.
332 Some registers can autoindex
333 Postindexing: Performed after indirection
334 Preindexing: Indexing is performed before indirection.

13.8 Stack Addressing: The stack pointer is maintained in a register. Thus, refer-
ences to stack locations in memory are in fact register indirect addresses.


14 - There is a huge amount of material about the specific instruction code
for a variety of hardware, most of which will never be seen again. I'm not
including it here. Needless to say, almost anything that can be done to
instruction sets has been done, from adding access coding schemes to having
variable sized instructions/


15 Assembly Language: Learning Assembler while standing on one foot.

15.1 A processor can understand and execute machine instructions.
11 Such instructions are simply binary numbers stored in the computer.
12 If a programmer wished to program directly in machine language, then it
would be necessary to enter the program as binary data and that sucks

121 Consider the simple BASIC statement
N = I + J + K

Suppose we wished to program this statement in machine language
and to initialize I, J, and K to 2, 3, and 4, respectively.
1211 The program starts in location 101 (hexadecimal). Memory
is reserved for the four variables starting at location 201.

1212 The program consists of four instructions:

1. Load the contents of location 201 into the AC.
2. Add the contents of location 202 to the AC.
3. Add the contents of location 203 to the AC.
4. Store the contents of the AC in location 204.


1213 This is clearly a tedious and very error-prone process.

1214 Use of Symbols makes it more doable.

15.2 Assembler : A much better system, and one commonly used, is to use symbolic addresses.
Each line still consists of three fields. The first field is still for the address, but a
symbol is used instead of an absolute numerical address. Some lines have no address,
implying that the address of that line is one more than the address of the previous line.
For memory-reference instructions, the third field also contains a symbolic address.


  1. 2014-12-02 Ruben <ruben.safir-at-my.liu.edu> Subject: [LIU Comp Sci] Arch Study tonight
  2. 2014-12-02 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Memory Notes et al
  3. 2014-12-02 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Re: Sorry for the last reply
  4. 2014-12-06 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] All the notes through External Memory
  5. 2014-12-06 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] Parity Bit Algebra
  6. 2014-12-06 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Parity Bit Algebra
  7. 2014-12-06 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] Parity Bit Algebra
  8. 2014-12-06 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Parity Bit Algebra
  9. 2014-12-06 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Parity Bit Algebra
  10. 2014-12-06 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] Parity Bit Algebra
  11. 2014-12-06 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Parity Bit Algebra
  12. 2014-12-06 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] Parity Bit Algebra
  13. 2014-12-06 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Parity Bit Algebra
  14. 2014-12-06 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Parity Bit Algebra
  15. 2014-12-06 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] Parity Bit Algebra
  16. 2014-12-06 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Parity Bit Algebra
  17. 2014-12-06 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Parity Bit Algebra
  18. 2014-12-06 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] Parity Bit Algebra
  19. 2014-12-06 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] Parity Bit Algebra
  20. 2014-12-06 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Parity Bit Algebra
  21. 2014-12-06 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Parity Bit Algebra
  22. 2014-12-06 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] All the notes through External Memory
  23. 2014-12-06 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Parity Bit Algebra
  24. 2014-12-07 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] Computer Available
  25. 2014-12-07 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Computer Available
  26. 2014-12-07 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Computer Available
  27. 2014-12-07 mrbrklyn-at-panix.com Subject: [LIU Comp Sci] Upcoming Events for Oracle Professionals
  28. 2014-12-08 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] Memorize Optcode
  29. 2014-12-08 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Memorize Optcode
  30. 2014-12-08 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] Memorize Optcode
  31. 2014-12-08 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Memorize Optcode
  32. 2014-12-08 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] Memorize Optcode
  33. 2014-12-08 Kamran <kamran.mirzayev-at-my.liu.edu> Re: [LIU Comp Sci] Memorize Optcode
  34. 2014-12-08 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Memorize Optcode
  35. 2014-12-08 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Memorize Optcode
  36. 2014-12-08 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] Memorize Optcode
  37. 2014-12-08 Ruben <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Memorize Optcode
  38. 2014-12-08 Ruben <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Memorize Optcode
  39. 2014-12-08 Ruben <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Memorize Optcode
  40. 2014-12-08 Kamran <kamran.mirzayev-at-my.liu.edu> Re: [LIU Comp Sci] Memorize Optcode
  41. 2014-12-08 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] UPerclassmen
  42. 2014-12-08 Ruben <ruben.safir-at-my.liu.edu> Re: [LIU Comp Sci] UPerclassmen
  43. 2014-12-08 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] UPerclassmen
  44. 2014-12-08 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] UPerclassmen
  45. 2014-12-08 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Arch Problem Solution for the final HW question
  46. 2014-12-08 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Foundation for OPTCODE and Machine Instruction
  47. 2014-12-08 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Memorize Optcode
  48. 2014-12-08 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Notes Done on In and Out, Operating Systemsm Modules and Memoery
  49. 2014-12-08 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] UPerclassmen
  50. 2014-12-09 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Anyone in school
  51. 2014-12-09 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] CPU Instructions - Notes for Chapter 14
  52. 2014-12-09 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Machine Instructions notes
  53. 2014-12-09 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Relative - PC addressing
  54. 2014-12-09 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] wifi
  55. 2014-12-10 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Answers to the final review questions
  56. 2014-12-10 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] database Hoem Work
  57. 2014-12-10 duodujames <duodujames-at-gmail.com> RE: [LIU Comp Sci] noone in class?
  58. 2014-12-10 Ruben <ruben.safir-at-my.liu.edu> Re: [LIU Comp Sci] UPerclassmen
  59. 2014-12-10 Maneesh Kongara <maneeshkongara-at-gmail.com> Subject: [LIU Comp Sci] Answers to the final review questions
  60. 2014-12-10 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] database Hoem Work
  61. 2014-12-10 Ruben <ruben.safir-at-my.liu.edu> Subject: [LIU Comp Sci] Fwd: MINIPROJECT
  62. 2014-12-10 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] HW 6
  63. 2014-12-10 mrbrklyn-at-panix.com Subject: [LIU Comp Sci] MINIPROJECT
  64. 2014-12-10 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] noone in class?
  65. 2014-12-10 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] welcome jame
  66. 2014-12-10 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] [mrbrklyn-at-panix.com: HW Last one maybe 6?]
  67. 2014-12-11 Ruben Safir <mrbrklyn-at-panix.com> Fwd: Re: [LIU Comp Sci] Database Class concepts which are still unclear
  68. 2014-12-11 Ruben Safir <mrbrklyn-at-panix.com> Re: Fwd: Re: [LIU Comp Sci] Database Class concepts which are still
  69. 2014-12-11 Ruben <ruben.safir-at-my.liu.edu> Re: [LIU Comp Sci] Database Class concepts which are still unclear
  70. 2014-12-11 Ruben <ruben.safir-at-my.liu.edu> Re: [LIU Comp Sci] Database Class concepts which are still unclear
  71. 2014-12-11 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Database Class concepts which are still unclear
  72. 2014-12-11 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Database Class concepts which are still unclear
  73. 2014-12-11 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Fwd: Invitation: Flatiron Alumni Present!
  74. 2014-12-11 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Fwd: Re: Database Class concepts which are still unclear
  75. 2014-12-11 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Fwd: turning attibute values into relations?
  76. 2014-12-11 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] jobs
  77. 2014-12-12 James Kwabena Duodu <duodujames-at-gmail.com> Re: [LIU Comp Sci] Answers to the final review questions
  78. 2014-12-12 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] .NET and C# free implimentation
  79. 2014-12-12 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Calling Upper Classman
  80. 2014-12-12 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Fwd: Re: n-ary operations
  81. 2014-12-12 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Fwd: Re: Oracle XE Web Server
  82. 2014-12-12 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Fwd: Re: relational algrabra division?
  83. 2014-12-12 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] jobs
  84. 2014-12-12 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] lerning tools
  85. 2014-12-12 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] liu mailing list
  86. 2014-12-12 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Re: turning attibute values into relations?
  87. 2014-12-12 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Sunday Arch Finals Review Study Session
  88. 2014-12-13 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Answers to the final review questions
  89. 2014-12-13 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] (fwd) Re: relational algrabra division?
  90. 2014-12-13 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Base Conversations
  91. 2014-12-13 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Gates HW problems
  92. 2014-12-13 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Logic Gates
  93. 2014-12-13 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] old homework question
  94. 2014-12-14 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Answers to the final review questions
  95. 2014-12-14 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] NOTE ERROR:****Error in the Hamming notes on the final review
  96. 2014-12-15 Ruben <ruben.safir-at-my.liu.edu> Re: [LIU Comp Sci] Answers to the final review questions
  97. 2014-12-15 Kamran <kamran.mirzayev-at-my.liu.edu> Re: [LIU Comp Sci] study hall today
  98. 2014-12-15 Ruben <ruben.safir-at-my.liu.edu> Re: [LIU Comp Sci] study hall today
  99. 2014-12-15 Kamran <kamran.mirzayev-at-my.liu.edu> Re: [LIU Comp Sci] study hall today
  100. 2014-12-15 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] study hall today
  101. 2014-12-15 Kamran <kamran.mirzayev-at-my.liu.edu> Re: [LIU Comp Sci] study hall today
  102. 2014-12-15 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] study hall today
  103. 2014-12-15 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] study hall today
  104. 2014-12-15 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] study hall today
  105. 2014-12-15 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] study hall today
  106. 2014-12-15 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] study hall today
  107. 2014-12-15 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] study hall today
  108. 2014-12-15 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] errror in the hamming notes.
  109. 2014-12-15 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] [Samir.Iabbassen-at-liu.edu: RE: NOTE ERROR:****Error in the Hamming
  110. 2014-12-16 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Study Hall
  111. 2014-12-16 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Study Hall
  112. 2014-12-16 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] [mrbrklyn-at-panix.com: HW Last one maybe 6?]
  113. 2014-12-17 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] database class
  114. 2014-12-17 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] database class
  115. 2014-12-17 James Kwabena Duodu <duodujames-at-gmail.com> Re: [LIU Comp Sci] database class
  116. 2014-12-17 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] database class
  117. 2014-12-17 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] database class
  118. 2014-12-17 duodujames <duodujames-at-gmail.com> Re: [LIU Comp Sci] database class
  119. 2014-12-17 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] database class
  120. 2014-12-17 James Kwabena Duodu <duodujames-at-gmail.com> Re: [LIU Comp Sci] database class
  121. 2014-12-17 Maneesh Kongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] database class
  122. 2014-12-17 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] database class
  123. 2014-12-17 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] database class
  124. 2014-12-17 Ruben <ruben.safir-at-my.liu.edu> Re: [LIU Comp Sci] database class
  125. 2014-12-17 Ruben <ruben.safir-at-my.liu.edu> Re: [LIU Comp Sci] study hall today
  126. 2014-12-17 Kamran <kamran.mirzayev-at-my.liu.edu> Re: [LIU Comp Sci] study hall today
  127. 2014-12-17 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] why is this textbook just off the look
  128. 2014-12-17 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] why is this textbook just off the look
  129. 2014-12-17 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] database class
  130. 2014-12-17 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Fwd: Database HW6
  131. 2014-12-17 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] the silence
  132. 2014-12-17 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Traffic Lights Diagram
  133. 2014-12-17 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] why is this textbook just off the look
  134. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] in coming
  135. 2014-12-18 Ruben <ruben.safir-at-my.liu.edu> Re: [LIU Comp Sci] Need tutoring on Relational Calculus
  136. 2014-12-18 Ruben <ruben.safir-at-my.liu.edu> Re: [LIU Comp Sci] Need tutoring on Relational Calculus
  137. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Need tutoring on Relational Calculus
  138. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Need tutoring on Relational Calculus
  139. 2014-12-18 Sergei Glikstein <serge.gl-at-gmail.com> Re: [LIU Comp Sci] Normalization review
  140. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Normalization review
  141. 2014-12-18 Sergei Glikstein <serge.gl-at-gmail.com> Re: [LIU Comp Sci] Normalization review
  142. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Normalization review
  143. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Normalization review
  144. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Normalization review
  145. 2014-12-18 maneeshkongara <maneeshkongara-at-gmail.com> Re: [LIU Comp Sci] Normalization review
  146. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Normalization review
  147. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Normalization review
  148. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Normalization review
  149. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Normalization review
  150. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Normalization review
  151. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Normalization review
  152. 2014-12-18 Sergei Glikstein <serge.gl-at-gmail.com> Re: [LIU Comp Sci] Normalization review
  153. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Normalization review
  154. 2014-12-18 From: <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Normalization review
  155. 2014-12-18 Sergei Glikstein <serge.gl-at-gmail.com> Re: [LIU Comp Sci] Normalization review
  156. 2014-12-18 From: <mrbrklyn-at-panix.com> Re: [LIU Comp Sci] Normalization review
  157. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] BCNF
  158. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] in coming
  159. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] lunch
  160. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Need tutoring on Relational Calculus
  161. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Normalization review
  162. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Re: relational calculus
  163. 2014-12-18 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] relational calculus
  164. 2014-12-19 Ruben <ruben.safir-at-my.liu.edu> Subject: [LIU Comp Sci] Oracle Files for the Homework and Oracle Resources
  165. 2014-12-22 Ruben <ruben.safir-at-my.liu.edu> Subject: [LIU Comp Sci] Operating Systems Class
  166. 2014-12-30 Ruben Safir <mrbrklyn-at-panix.com> Subject: [LIU Comp Sci] Creating a New OS: Final Projects for MS degree

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