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| DATE | 2015-02-01 |
| FROM | Ruben
|
| SUBJECT | Subject: [LIU Comp Sci] DMA memory and CPU activity
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From owner-learn-outgoing-at-mrbrklyn.com Sun Feb 1 11:24:32 2015
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Message-ID: <54CE533D.1040107-at-my.liu.edu>
Date: Sun, 01 Feb 2015 11:24:29 -0500
From: Ruben
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To: Samir Iabbassen , learn-at-nylxs.com,
Mohammed Ghriga
Subject: [LIU Comp Sci] DMA memory and CPU activity
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Dr Samir
I still have complaints ;)
Remember where it was taught and it was actually on exams , that when
the DMA memory controller copied blocks of data to main memory, then the
CPU, which lost control of the memory bus, was interrupted and not
active, and I read that in the book and saw it in the notes and but
still thought, No way. We disagreed in class and according to the
notes, you were 100% correct. But it didn't make sense. Its not that
useful to have DMA talking to memory and then the CPU not doing other
stuff in parallel.
I'm still at a loss on this matter... really, at minimum there is local
memory cache with the blocks of cache memory which it can work with, and
it just makes zero sense to have 4 or even 8 CPUs if they can't work in
parrelel with DMA activities.
Now, check this out from the operating systems class:
QUOTE:
To start an I/O operation, the device driver loads the appropriate registers
within the device controller. The device controller, in turn, examines the
contents of these registers to determine what action to take (such as “read
a character from the keyboard”). The controller starts the transfer of
data from
the device to its local buffer. Once the transfer of data is complete,
the device
controller informs the device driver via an interrupt that it has
finished its
operation. The device driver then returns control to the operating system,
possibly returning the data or a pointer to the data if the operation
was a read.
For other operations, the device driver returns status information.
This form of interrupt-driven I/O is fine for moving small amounts of data
but can produce high overhead when used for bulk data movement such as disk
I/O . To solve this problem, direct memory access (DMA) is used. After
setting
up buffers, pointers, and counters for the I/O device, the device controller
transfers an entire block of data directly to or from its own buffer
storage to
memory, with no intervention by the CPU. Only one interrupt is generated per
block, to tell the device driver that the operation has completed,
rather than
the one interrupt per byte generated for low-speed devices. While the device
controller is performing these operations, the CPU is available to
accomplish
other work.
Some high-end systems use switch rather than bus architecture. On these
systems, multiple components can talk to other components concurrently,
rather than competing for cycles on a shared bus. In this case, DMA is even
more effective. Figure 1.5 shows the interplay of all components of a
computer
system.
OPERATING
SYSTEM
CONCEPTS
ABRAHAM SILBERSCHATZ
Yale University
PETER BAER GALVIN
Pluribus Networks
GREG GAGNE
Westminster College
So now I am even MORe confused than before....
Any light you can shed?
Ruben
cc Dr Ghira, Learn
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