MESSAGE
| DATE | 2015-02-04 |
| FROM | Ruben Safir
|
| SUBJECT | Subject: [LIU Comp Sci] (fwd) Re: Operating System Design
|
From owner-learn-outgoing-at-mrbrklyn.com Wed Feb 4 13:23:19 2015
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From: Ruben Safir
To: learn-at-nylxs.com
Subject: [LIU Comp Sci] (fwd) Re: Operating System Design
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From: ruben safir
Newsgroups: comp.os.linux.hardware
Subject: Re: Operating System Design
Date: Sun, 01 Feb 2015 19:34:48 -0500
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Xref: panix comp.os.linux.hardware:364729
On 01/30/2015 03:00 AM, David Brown wrote:
> On 29/01/15 23:11, ruben safir wrote:
>> I'm wondering if anyone has a background in operating system design.
>> I'm taking a class is OS's and the text is
>>
>> OPERATING
>> SYSTEM
>> CONCEPTS
>> ABRAHAM SILBERSCHATZ
>> 9th edition, and it says something that is puzzling me
>>
>>
>>
>> "Interrupts are an important part of a computer architecture. Each
>> computer design has its own interrupt mechanism, but several functions
>> are common. The interrupt must transfer control to the appropriate
>> interrupt service routine. The straightforward method for handling this
>> transfer would be to invoke a generic routine to examine the interrupt
>> information. The routine, in turn, would call the interrupt-specific
>> handler. However, interrupts must be handled quickly"
>>
>> " Since only a predefined number of interrupts is possible, a table of
>> pointers to interrupt routines can be used instead*** to provide the
>> necessary speed. The interrupt routine is called indirectly through the
>> table, with no intermediate routine needed. Generally, the table of
>> pointers is stored in low memory (the first hundred or so locations).
>> These locations hold the addresses of the interrupt service routines for
>> the various devices. This array, or interrupt vector, of addresses is
>> then indexed by a unique device number, given with the interrupt
>> request, to provide the address of the interrupt service routine for
>> the interrupting device. Operating systems as different as Windows and
>> UNIX dispatch interrupts in this manner."
>>
>>
>> *** Instead of what? Just because you have a table of pointers to
>> routines doesn't change the need for a routine, a generic routine
>> perhaps, from accessing that table.
>>
>
> When a cpu receives an unmasked interrupt signal (you will probably
> learn about masking interrupts later - generally, the OS can control
> which interrupts are enabled), it must do three things:
>
> 1. It must pause execution of the current instruction stream
> 2. It must store critical state data so that normal execution can be
> resumed later.
> 3. It must jump to some user/system code to handle the interrupt.
>
> Step 1 here is mostly internal to the processor, and won't be visible to
> the OS or programmers (except that it can affect the reaction time for
> interrupts, which can be critical in embedded systems).
>
> Step 2 varies tremendously between processor types, but it generally
> involves storing a minimal set of registers in a safe place, so that the
> software interrupt handler can run (and save other registers as needed).
> CISC processors generally push the current stack pointer and the flag
> register onto the stack. For more complex CISC processors such as the
> 68040, there can be other registers saved to keep track of the state of
> long-running instructions (like block copy instructions). RISC
> processors like the PPC save them in dedicated "interrupt save"
> registers. Some processors, like the ARM responding to a "fast
> interrupt", enable a dedicated register bank. And some, like the
> Cortex-M3, save a number of registers so that the interrupt handlers can
> be written as plain C functions without need for assembly or special
> handling.
>
> Step 3 is where the processor figures out what code to run next. This
> again varies between processors. For some, there is a single fixed
> address that is always used - then it is up to the user code to figure
> out the source of the interrupt, and handle it (using a table of
> function pointers, a switch statement, a series of if's, etc.). Some
> processors have dedicated internal registers for interrupt routine
> addresses. Some will have an interrupt controller module (either
> builtin, or as a separate device) that figures out the interrupt source
> and gets an appropriate handler address from internal registers or a
> memory table. And other cpus get an interrupt number directly, and use
> that to look up a table of handler addresses (typically based at a
> configurable address).
>
> However the handler address is discovered, the processor then jumps to
> the code at that address. It is up to that code to figure out what
> caused the interrupt (if the cpu supports a table of handlers, the code
> will already have a fair idea). It also needs to store additional
> registers and processor state, and then deal with the interrupt itself.
> Afterwards it can either return to the interrupted code, or cause some
> sort of context switch (a more advanced topic that you will get to later
> in the book, I expect).
>
> For most processors, this handler requires some assembly programming or
> at least special compiler extensions and attributes - it is not a
> "normal" C function. And there are always restrictions on how handler
> code interacts with the OS and system calls.
>
>
> A note on terminology - the term "interrupt vector" is sometimes used to
> mean a table of pointers to interrupt handlers, as used in the quotation
> you gave. But it can also be used to mean simply /a/ pointer to an
> interrupt handler. Thus sometimes one talks about "a table of interrupt
> vectors". I've tried to avoid the term here, to avoid confusion - I
> recommend you do so too unless you make the meaning explicitly clear.
>
>
>
Now it says later:
The interrupt-driven nature of an operating system defines that
system?s general structure. For each type of interrupt, separate
segments of code in the operating system determine what action should be
taken. An interrupt service routine is provided to deal with the
interrupt. Since the operating system and the users share the hardware
and software
~~~~~~~~~~~
You seem to explain it much better than they do. These poorly written
text books are getting me depressed.
-- end of forwarded message --
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