MESSAGE
| DATE | 2021-01-25 |
| FROM | Gavin Smith
|
| SUBJECT | Re: [Hangout - NYLXS] Future plans for Autotools
|
From hangout-bounces-at-nylxs.com Mon Jan 25 19:27:26 2021
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From: Gavin Smith
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Date: Mon, 25 Jan 2021 22:59:01 +0000
To: Paul Eggert
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Subject: Re: [Hangout - NYLXS] Future plans for Autotools
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On Mon, Jan 25, 2021 at 02:10:01PM -0800, Paul Eggert wrote:
> On 1/25/21 5:37 AM, Paul Smith wrote:
> > The only thing that would make much of a performance difference, I
> > think, is if we are able to replace lots of shell invocations with
> > built-in make functions like wildcard, if, etc.
>
> One other thing could be a significant performance win: if we could use GNU
> 'make -j' to run most of the guts of the 'configure' script in parallel.
> Waiting for 'configure' to finish is something that slows me down a lot;
> often times 'configure' takes longer than the subsequent 'make', simply
> because 'configure' is inherently sequential.
>
It could be worth explaining how exactly this works so that one test
or rule can use the results of another test.
For example, there would be some rule to build a file foo.o:
foo.o: foo.c
$(CC) -c foo.c
This depends on the value of CC being available, which with autoconf
is set with the AC_PROG_CC macro before make even runs. So maybe you have
foo.o: CC=$(shell cat CC.conf)
foo.o: foo.c CC.conf
$(CC) -c foo.c
CC.conf:
... checks for cc
storing the value that should be in CC in the file CC.conf. Does this
work or does GNU make have other ways of doing this? (It would be
better if it could be done without communicating via files.) Is there
any way to set a Makefile variable from within a rule and then depend upon
that variable being set in other rules?
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