|FROM ||Ruben Safir
|SUBJECT ||Subject: [NYLXS - HANGOUT] [LIU Comp Sci] Machine Instructions notes
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Date: Tue, 9 Dec 2014 03:44:00 -0500
From: Ruben Safir
Subject: [NYLXS - HANGOUT] [LIU Comp Sci] Machine Instructions notes
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This is up to assembler
I lose this guy half way through the slides and text. All of a sudden,
he is throwing this term around, Implicit, and never defining it.
I'm not thrilled with this text. He has sent me on the white rabbit
hunt before, trying to fill in the gaps of what is is saying. He is not
organized in his notes and paragraph structure. He just rambles, and so
do the notes then.
He goes through this whole specification on the x86 and the ARM and you
can spend a year on that...and tomorrow it will all be changed, if not
already changed. I wish he would stick to priniciples. You can always
apply the princiiples.
Machine Instructions and Optcodes
12.0 Elements of Machine Instructions
12.01 Operation Code:
.011 Specifies the operation to be performed
12.02 Source Operand Reference:
.021 Operation Inputs
12.03 Result Operand Reference:
.031 Where the result is stored if need be
12.04 Next Instruction Reference:
.032 Where the next instruction to execute is located
.033 The address can be real or virtual
12.1 Operand Sources:
12.11 Virtual or Main Memory
12.12 Processor Register
12.13 Immediate: The orperand is contained within a field of
the instruction being executed.
12.14 I/O device
12.15 Possible Instruction Layout
| Opcode | Operand Reference | Operant Reference|
4 bits 6 bits 6 bit
Total 16 bits
12.151 IR - Instruction Register is where the instruction is read to
on the Control Unit.
12.152 Symbolic Representation:
1525 LOAD Load Data from memory
1526 STOR Store Data to memory
1527 Operands can also be referred to symbolically
ADD R Y
12.2 Instruction capabilities and Types:
The instruction set must be sufficient to able to perform any operation
that the computer hardware is capable of, either singularly or in
combination with each other.
12.21 Data Processing: Arithmetic and Logical Operations
12.22 Data Storage: Move Data into and out of memory and registers
12.23 I/O instruction: Remember those feisty I/O modules?
12.24 Control - Test and Branch
12.3 Address References: Usually one might need to reference 4 addresses
in an instuction cycle: Two Source Operands, a destination for output
Operand and the next instruction to execute.
12.31 Solutions to specific problems can be solved with one, two or three (or
Y = A-B
C + (D*E)
.3112 Singular Operand - Assumes an Accumulator Register (AC)
.3113 Double Operand:
Y = A MOV Y,A
Y <- Y - B SUB Y, B
D <- D * E MPY D, E
D <- D + C ADD D, C
Y <- Y / D Y DIV T
.3114 Triple Operand
T = A - B SUB T, A, B
L = D * C MTY L, D, E
L = L + C ADD L,L,C
Y = T/L DIV Y,T,L
12.32 There are trade offs among the differing techniques.
321 Multiple Addresses allow for use of fast registers for data storage
322 Few operands allow for more primitive processors and small
323 More addresses might leverage an expanded opcode set and differing
324 STACKS can use zero address instructions
12.33 Operand Set Design Issues:
It may surprise you to know that some of the
most fundamental issues relating to the design
of instruction sets remain in dispute. Indeed,
in recent years, the level of disagreement
concerning these fundamentals has actually
grown. The most important of these fundamental
design issues include the following:
Operation repertoire: How many and which
operations to provide, and how complex operations
Data types: The various types of data upon which
operations are performed
Instruction format: Instruction length (in bits),
number of addresses, size of various fields,
and so on
Registers: Number of processor registers that
can be referenced by instructions, and their use
Addressing: The mode or modes by which the
address of an operand is specified
These issues are highly interrelated and must be
considered together in designing an instruction
set. This book, of course, must consider them
in some sequence, but an attempt is made to show
12.4 Data Type: Numbers,
12.412 Binary Integer or Binary Fixed Point
12.413 Binary Floating Point
4141 Packed Decimal
41411 Each decimal digit is represented by a 4-bit code
41412 0000 => 1001 which is 0 -> 9
41413 4-bit codes are strung together, usually
in multiples of 8 bits from 0 -> 9999
41414 0000 0000 0000 0000 -> 1001 1001 1001 1001
41415 Standard sign values are 1100 for positive ( +)
and 1101 for negative ( -)
12.421 International Reference Alphabet (IRA) - ASCII
12.422 unique 7-bit pattern
12.423 128 different characters
12.424 some of the patterns represent control characters
12.425 transmitted using 8 bits per character
12.426 IRA bit pattern 011XXXX, the digits 0 through 9 are
represented by their binary equivalents, 0000 through 1001
12.4261 This is the same as the pack code
12.43 Logic Data: - Bitwise arrays which store arrays of True or False
12.5 Architectural Example: x86
51 Byte, word (16 bits), doubleword (32 bits), quadword (64 bits), and
double quadword (128 bits) locations with arbitrary binary contents.
52 Integer: A signed binary value contained in a byte, word, or doubleword, using
twos complement representation.
53 Ordinal: An unsigned integer contained in a byte, word, or doubleword.
54 Unpacked binary coded decimal (BCD): A representation of a BCD digit in the range 0 through 9, with one
digit in each byte.
55 Near pointer: A 16-bit, 32-bit, or 64-bit effective address that represents the offset
within a segment. Used for all pointers in a nonsegmented memory and for references within a segment in a segmented memory.
56 Far pointer
A logical address consisting of a 16-bit segment selector and an offset
of 16, 32, or 64 bits. Far pointers are used for memory references in a
segmented memory model where the identity of a segment being
accessed must be specified explicitly.
57 Bit field
A contiguous sequence of bits in which the position of each bit is
considered as an independent unit. A bit string can begin at any bit
position of any byte and can contain up to 32 bits.
58 Bit string
A contiguous sequence of bits, containing from zero to 232 - 1 bits.
59 Byte string
A contiguous sequence of bytes, words, or doublewords, containing from
zero to 232 - 1 bytes.
5-10 Packed SIMD (single instruction, multiple data)
Packed 64-bit and 128-bit data types (MMX)
5-11 Floating Points:
Notice the 2's complements
12.6 Types of Operations:
.61 Data Transfer -
.63 Logical - ADD, OR, NOT, SHIFT, ROTATE etc
.64 Conversion - TRANSLATE, CONVERT
.65 I/O - INPUT, OUTPUT, TEST
.66 System Control - ??
.67 Transfer Control - Jump, Return, Execute
13.0 Address Modes:
.05 Register Indirect
13.1 The CPU has to determine with method it needs to use to interpret
13.11 Often, different opcodes will use different addressing modes.
13.12 One or more bits in the instruction format can be used as a
13.13 Effective Address: ==> without virtual memory it is the address in
Memory of a Register
13.131 In a virtual memory system, the effective address is a
virtual address or a register.
13.132 The actual mapping to a physical address is a function
of the memory management unit (MMU) and is invisible to the
13.2 Immediate Address Mode: Operand = A;
13.21 Most immediate form
13.22 Used to define constants, set initial values of variables
13.23 Typically numbers are assigned in Two's Compliment Form
13.24 When loaded into a data register, the signed bit is moved to the
extreme left of the word size.
13.25 In some cases, the immediate binary value is interpreted as an
unsigned nonnegative integer.
13.26 No memory reference other than the instruction fetch is required
to obtain the operand
13.27 The size of the number is restricted to the size of the address
field, which, in most instruction sets, is small compared with the
13.3 Direct Addressing: EA = A
13.31 The address field contains the effect address of the operand
13.32 Only one memory reference and no special calculation
----------------------------- [ ]
|[optcode]|[ A ]|==> [ Operand ] (location address stored in
----------------------------- [ ] A in the instruction )
13.4 Indirect Addressing: EA = (A)
13.41 Address field refers to the address of a word in memory, which in turn contains a full-length
address of the operand.
.411 This is a different mode than we have seen thus far. The total
addressing of the CPU is limited by the width of A. From there,
the total addressable memory locations can be extended by the
size of (2^ Word) by reading addresses from full memory locations
.412 Parenthesis means Contents Of => (A) is Contents within A
.412 If k is the number of bites of the Address Space A in the
instruction code, then although this method allows for access
of 2^N (where N is a Word Size), only 2^K addresses can be
accessed at any time (a subset of 2^N).
.413 In a virtual memory environment, all the effective address
locations can be confined to page 0 of any process, which can be
described within the limits of 2^K.
.414 When a process is active, there will be repeated references to
page 0, (inside a set of 2^K addreses) It therefor remains in real memory.
.4141 Thus, an indirect memory reference will involve, at most, one page
fault rather than two.
13.5 Register Addressing: EA = R
13.51 Similar to Direct Addressing
13.52 The operand is sitting in the register
13.53 Typically, an address field that references registers will have from 3 to 5 bits,
so that a total of from 8 to 32 general-purpose registers can be referenced.
13.54 In particular, suppose that the algorithm for twos complement multiplication were to
be implemented in software.
13.6 Register Indirect Addressing: EA = (R)
13.61 Same an indirect addressing but instead of reading a memory location
for an memory address that contains the operand, here well pull up a
register. The address in the register is a memory location for an
13.7 Displacement Addressing: EA = A + (R)
13.71 The Instruction has Two A fields
13.711 One of the A fields is explicit
13.712 The other is an implicit reference according to the optcode.
.7121 refers to a register whose contents are added to A to produce
the effective address.
7131 Relative Addressing or PC-Relative Addressing
311 Implicitly referenced register is a program counter
312 added to the Address field of the Instruct to form an EA
313 Address field is normally a two complement number for this
314 Thus, the effective address is a displacement relative to the
address of the instruction.
7132 Base register Addressing: The register contains a main memory
address and the A field is an offset.
321 Implements Segmentation
7133 Indexing - the opposite of register addressing where the
offset is in the register and A is the main memory location.
331 Efficient mechanism for performing iterative operations.
332 Some registers can autoindex
333 Postindexing: Performed after indirection
334 Preindexing: Indexing is performed before indirection.
13.8 Stack Addressing: The stack pointer is maintained in a register. Thus, refer-
ences to stack locations in memory are in fact register indirect addresses.
14 - There is a huge amount of material about the specific instruction code
for a variety of hardware, most of which will never be seen again. I'm not
including it here. Needless to say, almost anything that can be done to
instruction sets has been done, from adding access coding schemes to having
variable sized instructions/
15 Assembly Language: Learning Assembler while standing on one foot.
15.1 A processor can understand and execute machine instructions.
11 Such instructions are simply binary numbers stored in the computer.
12 If a programmer wished to program directly in machine language, then it
would be necessary to enter the program as binary data and that sucks
121 Consider the simple BASIC statement
N = I + J + K
Suppose we wished to program this statement in machine language
and to initialize I, J, and K to 2, 3, and 4, respectively.
1211 The program starts in location 101 (hexadecimal). Memory
is reserved for the four variables starting at location 201.
1212 The program consists of four instructions:
1. Load the contents of location 201 into the AC.
2. Add the contents of location 202 to the AC.
3. Add the contents of location 203 to the AC.
4. Store the contents of the AC in location 204.
1213 This is clearly a tedious and very error-prone process.
1214 Use of Symbols makes it more doable.
15.2 Assembler : A much better system, and one commonly used, is to use symbolic addresses.
Each line still consists of three fields. The first field is still for the address, but a
symbol is used instead of an absolute numerical address. Some lines have no address,
implying that the address of that line is one more than the address of the previous line.
For memory-reference instructions, the third field also contains a symbolic address.